IC Package Clock Control for Voltage Droop Mitigation

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Solution Overview

Problem

Integrated circuit (IC) packages face voltage droop issues due to increasing power requirements, leading to transient load conditions that exceed voltage droop thresholds, causing errors and faults, and existing solutions like adding layers increase manufacturing costs.

Innovation Solution

Implementing mitigation techniques by altering the start-up procedure and operating frequency of clock signals, and using mitigation circuitry to control transient load conditions and net voltage droop, reducing the need for additional design complexity and cost.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If additional layers are added to IC dies to increase voltage droop threshold, then voltage droop tolerance is improved, but manufacturing cost increases

Engineering Contradiction:

Improvevoltage droop toleranceVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent changes operational parameters (clock signal frequency, start-up procedure timing) to control transient load conditions and reduce voltage droop, avoiding the need for additional physical layers and reducing manufacturing cost while maintaining voltage droop tolerance

Inventive Principle:

Principle #35Parameter changes

2Power

If power requirements of IC dies are increased, then computational capability is improved, but transient load conditions worsen

Engineering Contradiction:

Improvecomputational capabilityVSAvoidtransient load conditions

Core Design Contradiction:

PowerVSReliability

Solution Approach 1:

The patent uses periodic clock gating and controlled start-up procedures to manage power consumption patterns, allowing high computational capability while controlling transient load conditions through periodic enablement and disablement of circuit blocks

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent implements preliminary voltage droop analysis during design and preliminary controlled start-up procedures to prevent excessive transient loads before they occur, ensuring reliability while maintaining high power capability

Inventive Principle:

Principle #10Preliminary action

3Speed

If clock signal frequency is increased, then processing speed is improved, but voltage droop increases

Engineering Contradiction:

Improveprocessing speedVSAvoidvoltage droop

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent dynamically adjusts clock signal frequency based on operational phase, using lower frequencies during start-up to reduce voltage droop and higher frequencies during normal operation to maintain processing speed, with smooth transitions between states

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS11950358B1Integrated circuit package with voltage droop mitigation

Publication Date: 2024.04.02 XILINX INC

AI summary

A semiconductor device system comprises an integrated circuit (IC) die. The IC die is configured to operate in a first operating mode during a first period, and a second operating mode during a second period. The first period is associated with enabling an element of the IC die and a first amount of voltage droop. The second period occurs after the first period and is associated with a second amount of voltage droop. The second amount of voltage droop is less than the first amount of voltage droop.