3D Chip Stacking in IC Packaging for Reduced Footprint
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Solution Overview
Problem
Current integrated circuit packaging systems face challenges in achieving simplified manufacturing processes, smaller dimensions, lower costs, increased functionality, and improved IO connectivity while maintaining reliability and performance.
Innovation Solution
The method involves stacking a vertical chip between two substrates, with the vertical chip being coupled to both substrates and encapsulated within a package body, allowing for more efficient use of space and improved interconnectivity, thereby enhancing the integration of circuitry and reducing package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional planar packaging is used, then manufacturing process is simple, but package size is large and IO connectivity is limited
Solution Approach 1:
The patent transitions from traditional planar (2D) packaging to three-dimensional (3D) chip stacking architecture. Multiple chip stacks are arranged vertically and connected via through-substrate vias, enabling increased IO connectivity and reduced package footprint by utilizing the vertical dimension for component arrangement and interconnection.
2Quantity of substance
If more circuitry and electrical connections are added, then features and performance improve, but packaging size increases
Solution Approach 1:
The invention arranges multiple chip stacks vertically in the Z-direction rather than spreading them out in the XY-plane. This 3D stacking approach allows a higher density of circuitry and electrical connections within a smaller horizontal footprint, effectively increasing the amount of circuitry without proportionally increasing package size.
Solution Approach 2:
The patent implements a nested structure where chip stacks are positioned within a package body, with through-substrate vias penetrating the substrate to connect upper and lower chip stacks. This nesting arrangement allows multiple functional layers to be stacked vertically, maximizing the use of vertical space for circuitry integration.
3Reliability
If chip stacking is implemented, then IO connectivity increases, but manufacturing complexity increases
Solution Approach 1:
The patent divides the packaging system into discrete modular chip stacks, each comprising a chip, substrate, and support structure. These standardized modules can be manufactured independently and then assembled through precision alignment and bonding processes, making the complex 3D stacking manufacturing more manageable through modularization and standardization of components.
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: providing a first substrate; mounting an integrated circuit structure on the first substrate; mounting a second substrate on the integrated circuit structure; coupling a vertical chip to the first substrate and to the second substrate; and forming a package body for encapsulating the integrated circuit structure, the vertical chip, and a portion of the second substrate.