Integrated Circuit Packaging via Conductive Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional integrated circuit packaging methods require separate chip packaging, leading to increased geometric dimensions, high material usage, complex processes, and high production costs, along with thermomechanical stress issues due to different material characteristics.
Innovation Solution
An integrated circuit packaging method involving a substrate with circuit pins, connection through holes, and a conductive layer that connects device pins to circuit pins, using conductive bonding materials like solder balls or pastes, and electroplating, with an adhesive film and encapsulation layer for reliable and cost-effective packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chips are separately packaged and mounted on a circuit board, then each chip can be individually protected and connected, but the geometric dimension of the entire system increases and cannot be sufficiently miniaturized
Solution Approach 1:
Multiple separately packaged chips are merged into a single integrated package structure. The patent combines multiple chip packages with their respective circuit boards into one unified assembly, where the packages are arranged in an array and interconnected through conductive vias and traces on the circuit board, eliminating the need for separate mounting of individually packaged chips.
Solution Approach 2:
The circuit boards are nested within the integrated package structure. The patent embeds multiple circuit boards inside the package housing, with the boards arranged in layers and interconnected through conductive vias. This nesting approach allows the circuit boards to be contained within the package volume rather than extending externally.
2Reliability
If separate chip packaging is used with bonding or flip-chip connections, then reliable electrical connection is achieved, but the manufacturing process becomes complicated and production cost increases
Solution Approach 1:
Conductive vias are formed in the circuit board before the chips are mounted. The patent creates through-holes filled with conductive material in advance, establishing the electrical connection pathways before the chips are attached to the circuit board. This preliminary formation of conductive vias simplifies the subsequent assembly process.
Solution Approach 2:
The patent uses standardized package structures and circuit board layouts that can be replicated for multiple chips. The integrated package employs a modular design where identical package units are arranged in arrays, allowing for standardized manufacturing processes and reducing overall system complexity through repetition rather than customization.
3Ease of manufacture
If separate chip packaging with multiple materials is used, then connection functionality is achieved, but various thermomechanical stress problems are induced at the interface of materials with different characteristics
Solution Approach 1:
The patent reduces material interface complexity by using more homogeneous materials throughout the integrated package. The circuit boards and package housing use compatible materials with matched thermal expansion coefficients, and the conductive vias are filled with materials that are chemically and thermally compatible with the surrounding structures, minimizing thermomechanical stress at interfaces.
4Ease of operation
If conventional separate packaging method is used, then each chip can be individually connected to circuit board, but a large amount of materials is used and production cost is high
Solution Approach 1:
Multiple circuit boards are merged into a single integrated package structure. The patent combines several circuit boards that would traditionally be separate into one unified package, sharing common housing, interconnection structures, and mounting mechanisms. This merging reduces the total material required for packaging and interconnection.
Solution Approach 2:
The circuit board serves multiple functions simultaneously. The patent designs the circuit board to provide both electrical interconnection between chips and structural support for the entire package assembly. The conductive vias in the circuit board serve dual purposes as both electrical pathways and mechanical alignment features, reducing the need for separate components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces packaging costs and time, minimizes system thickness, enhances integration density, and reduces thermomechanical stress, allowing for efficient data communication without the need for additional circuit boards and heat soldering steps.
Implementation Method 1
a conductive layer is formed by bonding the conductive bonding material to the device pin and an inner wall of the connection through hole
Implementation Method 2
the conductive layer is formed by electroplating during the process of forming a conductive layer in the connection through hole by means of the second opening of the connection through hole
Data Source
AI summary
An integrated circuit packaging method, including: a top surface of a substrate, a bottom surface of the substrate, or the interior of the substrate is provided with circuit layers, and the circuit layers are provided with circuit pins; a component element is mounted on the substrate, and a surface of the component element facing the substrate is provided with component pins; connection through holes are formed on the substrate, the connection through holes are made to abut on the circuit pins, and a first opening of the connection through holes is abutted on the component pins; conductive layers are fabricated inside of the connection through holes by means of a second opening of the connection through holes, and the conductive layers electrically connect the component pins with the circuit pins.