Integrated Circuit Packaging with Fine Wiring Interconnects
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Solution Overview
Problem
Conventional integrated circuit packaging methods require significant space and materials, leading to high production costs and thermomechanical stress issues due to the use of multiple materials with different characteristics, limiting miniaturization and efficiency in data communication between chips.
Innovation Solution
An integrated circuit packaging structure featuring a substrate with a circuit layer and fine wirings, where chips are directly connected via fine pins and wirings, with an insulation patch to prevent interference, and a heat sink for efficient heat dissipation, allowing for high-speed and wide-bandwidth data communication while reducing material usage and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chips are separately packaged and mounted on a circuit board with bonding or flip-chip connections, then reliable electrical connection is achieved, but the geometric dimension of the entire system increases and production cost rises
Solution Approach 1:
The patent merges multiple chips into a single integrated package unit that is mounted as one component on the circuit board. The chips are interconnected via fine wirings within the package, eliminating the need for separate bonding or flip-chip connections for each chip, thus reducing the overall system dimension while maintaining connection reliability
Solution Approach 2:
The patent introduces a substrate with fine wirings as an intermediary component within the package. This substrate provides direct electrical pathways between chips using fine conductive lines (0.1-5 micrometers wide), replacing traditional bonding wires or flip-chip interconnections and reducing the space required for electrical connections
2Reliability
If chips are separately packaged and mounted on a circuit board, then individual chip protection is achieved, but the production cost increases due to large amount of materials and complicated process
Solution Approach 1:
The patent combines multiple chips and their protective packaging into a single integrated package unit. This reduces the total amount of packaging materials needed and simplifies the manufacturing process by allowing the entire assembly to be produced and tested as one unit before mounting on the circuit board, thereby reducing production costs
Solution Approach 2:
The patent uses a thin encapsulation layer to protect the chips and fine wirings within the package. This thin-film approach provides adequate protection while minimizing material usage and maintaining a compact structure, reducing both material costs and manufacturing complexity
3Adaptability or versatility
If multiple materials with different characteristics are used in separate chip packaging, then individual chip requirements are met, but thermomechanical stress problems are induced at interfaces
Solution Approach 1:
The patent combines multiple chips and materials into a single integrated package that is mounted on the circuit board as one unit. This unified structure allows for more uniform thermal and mechanical stress distribution across the package, reducing interface stress problems that occur when separately packaged chips are mounted together
Solution Approach 2:
The patent employs composite material structures within the package, including the substrate with fine wirings and the encapsulation layer, that are designed to have compatible thermal and mechanical properties. This reduces thermomechanical stress at interfaces by using materials with matched expansion coefficients and mechanical characteristics
4Reliability
If conventional packaging methods are used with bonding or flip-chip connections, then electrical connection is achieved, but data transmission bandwidth and speed between chips are limited
Solution Approach 1:
The patent uses a substrate with fine wirings as an intermediary that provides direct, high-speed electrical pathways between chips. The fine conductive lines (0.1-5 micrometers wide) on the substrate offer lower inductance and capacitance compared to traditional bonding wires or flip-chip interconnections, enabling faster data transmission while maintaining reliable electrical connection
Solution Approach 2:
The patent transitions from three-dimensional interconnections (bonding wires arching above the chip surface) to planar two-dimensional fine wiring patterns on the substrate. This dimensional change reduces the length and complexity of signal paths, improving data transmission speed and bandwidth between chips
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables miniaturization, reduces production costs, and enhances data transmission speed and bandwidth between chips, while maintaining high computing performance and flexibility, by using fine wirings and insulation patches to isolate and connect chips efficiently.
Implementation Method 1
a heat sink (heat dissipating device) is provided on each chip
Data Source
AI summary
An integrated circuit packaging structure and method are provided, the integrated circuit packaging structure includes: a substrate, the substrate being provided with a circuit layer and fine wiring; a chip, the chip being provided with a fine pin and a chip pin; the substrate is provided with at least two of said chips, a chip pin of at least one of said chips being electrically connected to the circuit layer; an insulation patch, the fine wiring being provided on the insulation patch, while the fine pin of the chip is electrically connected to the fine wiring, at least two of said chips being directly electrically connected by means of the fine wiring.