Integrated Circuit Packaging with Mold Chase Encapsulation

The patent transitions from conventional two-dimensional packaging layouts to a three-dimensional stacked package architecture. Multiple die are vertically stacked within a single package footprint, utilizing the vertical dimension to increase circuit capacity without expanding the horizontal area on the mounting surface. This dimensional change directly resolves the contradiction by enabling higher density while maintaining compact footprint.

The patent implements a nested structure where multiple die are stacked vertically within a single package envelope. The smaller die are positioned one above another, similar to nested dolls, allowing multiple functional units to occupy the same horizontal footprint. This nesting approach enables the package to contain more circuitry without increasing the external dimensions.

The patent introduces an intermediary encapsulation material that fills the spaces between stacked die and provides a continuous medium for electrical interconnects. This encapsulation acts as a mediator that enables reliable signal and power transmission between vertically stacked die, solving the interconnect overlap problem while maintaining high circuit density.

The patent employs composite packaging structures combining multiple materials including die attach adhesives, encapsulation resins, and interconnect materials. These composite materials provide both mechanical support and electrical functionality, enabling reliable interconnections between stacked die while maintaining compact packaging. The composite approach allows optimization of each material's properties for its specific function.

The patent resolves this contradiction by stacking die vertically in the Z-dimension rather than arranging them horizontally in the X-Y plane. This vertical stacking allows multiple die to share the same mounting footprint, effectively increasing circuit capacity without expanding the area occupied on the mounting surface. The vertical dimension becomes the primary direction for scaling circuit capacity.

The patent uses thin encapsulation films and flexible die attach adhesives to bind multiple die together in a compact vertical stack. These thin films allow tight integration of multiple die within a small volume, preventing excessive expansion of the package dimensions while accommodating increased circuit capacity through vertical stacking.

The patent applies preliminary underfill material to the substrate before stacking die, pre-positioning the encapsulation material in strategic locations. This preliminary action ensures that when final encapsulation occurs, the material flows efficiently to fill all void spaces between stacked die, eliminating air pockets and ensuring complete filling without requiring complex manufacturing steps.

The patent extracts and removes air bubbles and voids from the encapsulation material during the curing process through vacuum degassing or pressure cycling. This extraction process eliminates trapped air pockets that would compromise encapsulation quality, achieving void-free filling while maintaining a relatively simple manufacturing workflow.