IC Packaging Mold Gate with Encapsulant Disruption Patterns

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Solution Overview

Problem

Current integrated circuit packaging technologies face challenges with increasing clock rates, EMI radiation, thermal loads, second-level assembly reliability stresses, and cost, particularly in producing smaller, more robust packages with reduced warpage and improved performance for portable electronics.

Innovation Solution

The method involves forming a mold gate on a substrate, mounting an integrated circuit, and using an encapsulant with disruption patterns emanating from the mold gate to encapsulate the circuit, which reduces warpage and mechanical stress, and enhances thermal performance by allowing side horizontal injection and transfer molding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If conventional packaging methods are used, then manufacturing is simpler, but warpage and mechanical stress increase

Engineering Contradiction:
ImprovewarpageVSAvoidpackaging structure
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The encapsulant is divided into multiple regions with different properties: a first region with disruption patterns emanating from the mold gate and a second region without disruption patterns. This segmentation allows different portions of the encapsulant to serve different functions - the first region controls warpage and stress while the second region provides standard encapsulation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The encapsulant has non-uniform local properties through the disruption patterns that are concentrated in the first region. The disruption patterns create localized variations in material structure that specifically address warpage and mechanical stress in critical areas near the mold gate, while other regions maintain uniform properties.

Inventive Principle:
Principle #3Local quality

2Volume of moving object

If package size is reduced, then portability improves, but thermal management becomes more difficult

Engineering Contradiction:
Improvepackage sizeVSAvoidthermal load
Core Design Contradiction:
Volume of moving objectVSTemperature

Solution Approach 1:

The disruption patterns are arranged in specific geometric configurations (concentric circles, radial lines, grids) that create three-dimensional stress distribution and thermal pathways within the encapsulant. This dimensional structuring allows efficient heat dissipation in compact packages by creating multiple thermal conduction paths through the encapsulant material.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Manufacturing precision

If manufacturing precision is increased, then product quality improves, but manufacturing complexity increases

Engineering Contradiction:
Improvedefect reductionVSAvoidmold gate structure
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The disruption patterns are pre-formed into the encapsulant material during the molding process itself, rather than requiring subsequent processing steps. The encapsulant is injected with built-in disruption patterns that automatically align with the mold gate, eliminating the need for separate alignment or processing operations.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8859342B2Integrated circuit packaging system with substrate mold gate and method of manufacture thereof
Publication Date: 2014.10.14 STATS CHIPPAC MANAGEMENT PTE LTD
  • US8859342B2 patent drawing
  • US8859342B2 patent drawing
  • US8859342B2 patent drawing

AI summary

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a mold gate on an upper surface of the substrate; mounting an integrated circuit to the substrate; and forming an encapsulant encapsulating the integrated circuit, the encapsulant having disruption patterns emanating from the mold gate and underneath a bottom plane of the integrated circuit.