Lead Interlocking Mechanisms for IC Packaging Reliability

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Solution Overview

Problem

Current semiconductor packaging technologies face challenges with lead-frame based packages experiencing solder shorts and reliability issues due to loose leads, while BGA packages are costly and inefficient to manufacture, necessitating a solution for improved reliability and reduced footprint size.

Innovation Solution

The development of an integrated circuit packaging system featuring leads with serrations and overhang portions, along with upper and bottom contact plates, where the integrated circuit die is encapsulated, leaving the bottom portion exposed, to enhance interlocking mechanisms and prevent solder shorts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If lead-frame based packages are used, then manufacturing cost is reduced and efficiency is improved, but solder shorts occur and contact reliability is reduced

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidcontact reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The lead is divided into distinct segments including an upper portion, bottom portion, and intermediate portion with serrations. This segmentation allows the intermediate portion to provide mechanical interlocking with the molding compound while the upper and bottom portions maintain electrical contact functions, thereby preventing solder shorts while preserving manufacturing efficiency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The lead features asymmetric geometry with serrations on the intermediate portion that create an interlocking mechanism with the molding compound. This asymmetric design prevents the lead from pulling out or becoming loose, improving contact reliability without compromising the lead-frame manufacturing process.

Inventive Principle:
Principle #4Asymmetry

2Ease of operation

If leads are made loose for ease of assembly, then assembly is simplified, but leads pull out and form cracks reducing reliability

Engineering Contradiction:
Improveassembly easeVSAvoidcontact reliability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The serrations and interlocking features are pre-formed on the lead during the lead-frame manufacturing process, before assembly occurs. This preliminary action ensures that the lead is securely anchored to the molding compound from the outset, preventing later pull-out and crack formation while maintaining assembly simplicity.

Inventive Principle:
Principle #10Preliminary action

3Area of stationary object

If BGA packages are used, then footprint size is reduced, but manufacturing cost increases and efficiency decreases

Engineering Contradiction:
Improvepackage footprintVSAvoidmanufacturing efficiency
Core Design Contradiction:
Area of stationary objectVSEase of manufacture

Solution Approach 1:

The lead-frame structure is designed to serve multiple functions: it provides the mechanical support framework, contains the electrical contacts, and incorporates the interlocking serrations for secure attachment. This multi-functionality allows the package to achieve BGA-like compactness while maintaining lead-frame manufacturing efficiency.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8415205B2Integrated circuit packaging system with lead interlocking mechanisms and method of manufacture thereof
Publication Date: 2013.04.09 STATS CHIPPAC LTD
  • US8415205B2 patent drawing
  • US8415205B2 patent drawing
  • US8415205B2 patent drawing

AI summary

A method of manufacture of an integrated circuit packaging system includes: forming a lead having an upper portion and a bottom portion with a first overhang portion from a top surface of the upper portion and the lead also having serrations along upper vertical sides intersecting the top surface; forming an upper contact plate on the top surface; forming a bottom contact plate on a bottom surface of the bottom portion; attaching an integrated circuit die over the upper portion; and encapsulating the upper portion and the integrated circuit die with an encapsulation leaving the bottom portion exposed.