Integrated Circuit Packaging with On-Die Passive Components

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Solution Overview

Problem

Conventional IC packaging methods result in increased parasitic resistances and inductances due to extended signal transmission paths, which are problematic in high-speed applications like ADCs, where minimizing time delay and maximizing operating frequency are crucial.

Innovation Solution

The method involves depositing conductive layers over integrated circuit dice, removing excess layers to expose bond pads, positioning passive components directly on the dice, and reflowing solder to connect them, thereby reducing signal transmission path lengths and enhancing electrical performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If passive components are mounted on PCB with extended traces, then ease of manufacture is improved, but parasitic resistances and inductances increase

Engineering Contradiction:

Improveease of manufactureVSAvoidparasitic resistances and inductances

Core Design Contradiction:

Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The patent merges the IC die and passive components into a single integrated package structure. The passive components are mounted directly on the IC die surface and encapsulated together, eliminating the need for separate PCB mounting and reducing the number of discrete components in the system.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from a planar PCB layout to a three-dimensional integrated structure. Passive components are positioned in the vertical dimension above the IC die, allowing signal paths to be shortened by routing signals vertically through bumps rather than horizontally across PCB traces.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Ease of operation

If signal transmission paths are extended to include PCB traces and passive components, then ease of operation is improved, but time delay increases

Engineering Contradiction:

Improveease of operationVSAvoidtime delay

Core Design Contradiction:

Ease of operationVSLoss of time

Solution Approach 1:

The IC die, passive components, and encapsulation are merged into a single integrated unit, dramatically shortening the signal transmission path from the IC output to the passive component and eliminating long PCB traces, thereby reducing time delay.

Inventive Principle:

Principle #5Merging (Combining)

3Productivity

If IC devices are miniaturized, then productivity is improved, but manufacturing precision requirements increase

Engineering Contradiction:

ImproveproductivityVSAvoidmanufacturing precision

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent performs preliminary actions by forming bump structures and depositing conductive layers on the IC die before mounting passive components. This sequence of pre-prepared structures facilitates precise alignment and reduces the complexity of subsequent assembly steps, enabling miniaturization while maintaining manufacturability.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach minimizes signal transmission path lengths, reducing parasitic resistances and inductances, thereby improving the electrical performance and miniaturizing IC devices, especially in high-speed applications.

Implementation Method 1

The solder is then reflowed to electrically and physically connect the electrodes of the non-active electrical component with the ones of the first set of bond pads

Methodology Applied

Scientific EffectSoldering: Soldering

Implementation Method 2

A first conductive layer is deposited over the active surfaces of the dice. Subsequently, a second conductive barrier layer is then deposited over the first conductive layer. A third solder-wettable conductive layer is then deposited over the second conductive barrier layer

Methodology Applied

Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Data Source

PatentUS7615407B1Methods and systems for packaging integrated circuits with integrated passive components

Publication Date: 2009.11.10 NAT SEMICON CORP

AI summary

A method is described for packaging integrated circuit dice such that each package includes a die with an integrated passive component mounted to the active surface of the die.