Integrated Circuit Packaging With Segmented Connection Layer
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Solution Overview
Problem
Modern electronics require more integrated circuits in a shrinking physical space with decreasing costs, but existing technologies fail to fully address the need for lower height, smaller size, and cost reduction while maintaining functionality.
Innovation Solution
The method involves forming a lead with a horizontal ridge, a connection layer with inner and outer pads on the lead top side, mounting an integrated circuit over the inner pad, applying a molding compound, and a dielectric on the molding and inner pad bottom surfaces, which simplifies the packaging process and reduces costs by eliminating lead pullouts and solder issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If existing manufacturing processes are reused, then manufacturing cost is reduced, but package dimensions cannot be reduced
Solution Approach 1:
The patent segments the connection layer into inner pads and outer pads with distinct functions. Inner pads provide electrical connection to the integrated circuit, while outer pads provide mechanical support and additional electrical connections. This segmentation allows optimization of each region independently, enabling cost-effective manufacturing with reduced package dimensions by eliminating unnecessary structural elements like lead pullouts.
Solution Approach 2:
The patent merges the electrical connection function and mechanical support function into a single integrated connection layer structure. The inner and outer pads work together as a unified system, eliminating the need for separate lead pullout structures. This merging simplifies the manufacturing process while achieving compact package dimensions.
2Adaptability or versatility
If more integrated circuits are integrated into each package, then functionality is improved, but package size increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration. Multiple integrated circuits are vertically stacked and connected through the inner and outer pads, enabling increased functionality within a compact footprint. This vertical integration significantly reduces package size while maintaining or enhancing functionality.
Solution Approach 2:
The patent implements a nested structure where multiple integrated circuits are stacked vertically, with each circuit nested within the overall package structure. The connection layer with inner and outer pads provides the interconnection framework that enables this nested arrangement, allowing multiple functional units to coexist in a compact volume.
3Device complexity
If traditional packaging structures are used, then manufacturing simplicity is maintained, but reliability is reduced due to lead pullouts and solder issues
Solution Approach 1:
The patent eliminates the use of traditional lead pullout structures and solder joints that are prone to failure. Instead, it employs a robust connection layer with inner and outer pads that provide reliable mechanical and electrical connections without the reliability issues associated with traditional solder-based assemblies. This approach sacrifices the simplicity of traditional processes but gains significant reliability.
Solution Approach 2:
The patent employs a coplanar arrangement of inner and outer pads that creates a distributed, resilient connection system. The pads are positioned to work together as an integrated system, providing redundancy and distributing mechanical and electrical stresses, thereby enhancing reliability compared to point-to-point solder connections.
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: forming a lead having a horizontal ridge at a lead top side; forming a connection layer having an inner pad and an outer pad directly on the lead top side, the inner pad having an inner pad bottom surface; mounting an integrated circuit over the inner pad; applying a molding compound, having a molding bottom surface, over the integrated circuit, the inner pad, and the outer pad; and applying a dielectric directly on the molding bottom surface and the inner pad bottom surface.