Integrated Circuit Packaging via Substrate Through-Holes
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Solution Overview
Problem
Conventional integrated circuit packaging methods are complex, costly, and limited by thermo-mechanical stresses and geometric constraints, hindering miniaturization and increasing production costs due to the use of multiple materials with different characteristics.
Innovation Solution
An integrated circuit packaging method involving a substrate with a circuit layer and connection through holes, where conductive layers are formed to electrically connect device pins to circuit pins, reducing material usage and eliminating the need for wire bonding or flip-chip methods, and allowing for flexible circuit boards and stacked arrangements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wire bonding or flip-chip methods are used to attach chips to circuit boards, then electrical connection between chips and circuit board is achieved, but the packaging process becomes complicated and production cost increases
Solution Approach 1:
The patent extracts and eliminates the intermediate circuit board from the traditional chip packaging system. By forming conductive layers directly on the chip surface and creating through-holes that pass through the chip substrate, the electrical connection is achieved without requiring separate wire bonding or flip-chip attachment to a circuit board, thereby simplifying the packaging process while maintaining connection reliability
Solution Approach 2:
The patent merges the electrical connection function and mechanical support function into a single integrated structure. The through-holes with conductive layers serve both as electrical pathways and as structural elements that directly connect the chip to the substrate, eliminating the need for separate bonding processes and reducing overall packaging complexity
2Reliability
If a large number of materials with different characteristics are used in packaging, then electrical connection and mechanical support are achieved, but thermo-mechanical stresses are induced at material interfaces
Solution Approach 1:
The patent uses the same material for both the substrate and the chip structure, creating a homogeneous packaging system. This eliminates the thermo-mechanical stress issues that arise from interfaces between dissimilar materials with different thermal expansion coefficients and mechanical properties, while still achieving reliable electrical and mechanical connections through the integrated through-hole structure
3Reliability
If sufficient space is maintained between chips and other electronic devices, then wire bonding and flip-chip connections can be implemented, but the geometric size of the entire system cannot be sufficiently miniaturized
Solution Approach 1:
The patent transitions from a planar packaging approach to a three-dimensional integrated structure by forming through-holes that penetrate the chip substrate vertically. This allows electrical connections to be made in the vertical dimension rather than requiring lateral space for wire bonds, enabling significant miniaturization of the system while maintaining reliable electrical connections
Solution Approach 2:
The patent implements a nested structure where the conductive layers are embedded within the through-holes that pass through the chip substrate. This nested arrangement allows the electrical connection pathway to be contained within the chip structure itself, eliminating the need for external wire bonds and reducing the overall system volume
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the packaging process, reduces costs, and enables miniaturization by eliminating the need for additional space between components, improving reliability and data communication speed while minimizing thermo-mechanical stresses.
Implementation Method 1
The conductive layer is formed by bonding the conductive bonding material to the inner wall of the connecting through hole and the device pin
Implementation Method 2
the conductive layer is formed by means of electroplating during the process of forming a conductive layer in the connection through hole
Data Source
AI summary
An integrated circuit packaging method and an integrated packaging circuit, the integrated circuit packaging method including: circuit layers are provided on the top surface of a substrate, the bottom surface of the substrate or the interior of the substrate, the circuit layers having circuit pins; the substrate is provided with connection through holes, and the connection through holes are joined up with the circuit pins; a device is placed on the substrate, and the device is provided with device pins on a surface facing the substrate, which makes the device pins join up with a first opening of the connection through holes; conductive layers are fabricated in the connection through holes by means of a second opening of the connection through holes; and the conductive layers electrically connect the device pins to the circuit pins.