IC Packaging with Vertical Vias for High-Density I/O
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Solution Overview
Problem
The increasing demand for miniaturization in integrated circuit packaging poses challenges in achieving high-density input/output (I/O) connections, leading to manufacturing issues such as fine pitch connections and reliability concerns, while also requiring cost-effective and efficient packaging solutions.
Innovation Solution
The integrated circuit packaging system involves forming external interconnects, planar terminals, and encapsulations to create a configuration where external interconnects extend from non-horizontal sides of the encapsulation, allowing for high-density I/O connections while maintaining reliability and cost-effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional molding processes are used to encapsulate the semiconductor die and lead frame, then the package structure is simplified and manufacturing is easier, but the I/O density is limited and fine pitch connections are difficult to achieve
Solution Approach 1:
The patent transitions from planar I/O connections to three-dimensional vertical connections by forming conductive vias through the molding compound. This allows I/O signals to be routed vertically through the package thickness, enabling fine pitch connections without increasing lateral complexity. The via-based interconnect structure resolves the contradiction by adding a vertical dimension to the interconnection architecture.
Solution Approach 2:
The patent segments the I/O connection function into multiple independent via structures distributed throughout the molding compound. Rather than relying on a single planar connection layer, the I/O paths are divided into multiple vertical via segments that can be independently formed and positioned, enabling precise control over connection pitch and improving manufacturing reliability.
2Adaptability or versatility
If the number of I/O connections is increased to provide greater functionality, then the device functionality is improved, but the package size increases and miniaturization is compromised
Solution Approach 1:
The patent utilizes the vertical dimension within the package thickness to accommodate multiple I/O connections. By routing signals through vertically extending vias rather than requiring lateral expansion, the design enables increased I/O count without proportionally increasing package footprint. This vertical interconnection approach allows high-density I/O integration within a compact three-dimensional volume.
Solution Approach 2:
The patent implements a nested interconnection architecture where conductive vias are embedded within the molding compound, and additional functional layers are integrated around these vias. This nested structure allows multiple I/O connections and support structures to be packed into the available volume efficiently, enabling high functionality within a minimized package envelope.
3Quantity of substance
If fine pitch connections are implemented to increase I/O density, then the I/O density is improved, but manufacturing complexity increases and reliability concerns arise
Solution Approach 1:
The patent performs preliminary formation of conductive vias through the molding compound before final package assembly and wire bonding. By pre-establishing the vertical interconnection pathways during the molding process itself, the subsequent wire bonding and assembly steps are simplified. This preliminary via formation reduces overall manufacturing complexity despite the fine pitch requirements.
Solution Approach 2:
The molding compound serves a dual function: it provides mechanical encapsulation and protection while simultaneously serving as the medium in which conductive vias are formed. The via formation process utilizes the molding compound's own material properties and processing conditions, eliminating the need for separate via drilling or etching steps. This self-service approach reduces manufacturing complexity while achieving high I/O density.
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: forming an external interconnect; forming a first planar terminal adjacent to the external interconnect and non-planar to a portion the external interconnect; mounting a first integrated circuit over the first planar terminal; connecting the first integrated circuit with the external interconnect; and forming an encapsulation over the first planar terminal covering the first integrated circuit and with the external interconnect extending from a non-horizontal side of the encapsulation and with the first planar terminal coplanar with the adjacent portion of the encapsulation exposing the first planar terminal.


