IC Pad Defect Testing via Internal Signal Routing
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Solution Overview
Problem
Integrated circuit testing at the die level is limited by physical test equipment constraints, such as the number of test probes, which often results in only partial testing and the potential for defects to go undetected, leading to defective dies being delivered and packaged.
Innovation Solution
Incorporating built-in testing enhancements within integrated circuits to test continuity and leakage current between externally accessible interconnects and internal circuitry, allowing for more thorough testing without direct contact with all pads, using techniques like routing test signals through metallization layers and coupling pads for simultaneous leakage current testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple test probes are used to test more pads, then testing coverage improves, but test equipment complexity and cost increase
Solution Approach 1:
The integrated circuit performs self-testing by using its own internal circuitry to test its pads. The circuit under test generates test signals and monitors its own pad connections, eliminating the need for external test equipment to directly probe each pad. This self-service approach resolves the contradiction by achieving complete testing coverage without requiring proportional increases in test equipment complexity.
Solution Approach 2:
The test circuit is integrated into the normal circuit functionality, allowing the same circuit to serve both operational purposes and testing purposes. The input buffers and pad structures are used for both normal signal processing and for detecting pad defects, achieving multi-functionality that resolves the contradiction between testing coverage and equipment complexity.
2Reliability
If all pads are tested individually with direct probe contact, then defect detection completeness improves, but testing time increases
Solution Approach 1:
Multiple pad tests are merged into a single integrated testing operation. The test circuit simultaneously or sequentially tests multiple pads through shared internal pathways, combining what would otherwise require separate probe contacts into a unified testing process. This merging approach achieves complete defect detection without proportionally increasing testing time.
Solution Approach 2:
The testing process is integrated into the continuous operation of the circuit rather than being a separate discontinuous process. The circuit can be tested during manufacturing without requiring separate testing stages, maintaining continuous productive action while achieving complete defect detection.
3Device complexity
If fewer test probes are used, then test equipment simplicity improves, but testing coverage decreases
Solution Approach 1:
The circuit under test serves its own testing needs by using internal signal generation and monitoring capabilities. This self-service mechanism allows complete testing coverage to be achieved with minimal external test equipment, resolving the contradiction by making the tested object itself the primary testing resource.
Solution Approach 2:
Internal circuit pathways and buffers serve as intermediaries between the limited external test probes and the multiple pads that need testing. These intermediary elements amplify and distribute test signals throughout the circuit, enabling comprehensive pad testing through fewer direct probe contacts.
4Productivity
If spot checking of selected pads is performed, then testing speed improves, but defect detection reliability decreases
Solution Approach 1:
The testing process maintains continuous operation without requiring slow sequential probing of each pad. The integrated test circuit continuously monitors all pads through internal pathways, achieving both high-speed testing and complete coverage simultaneously, thus resolving the contradiction between productivity and reliability.
Data Source
AI summary
Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads and/or leakage current testing for more than one pad. The disclosed techniques may permit more thorough testing of integrated circuits at the die level, thereby reducing the number of defective devices that are further processed, saving both time and money. In one embodiment, a test signal is routed in real time through a built-in path that includes an input buffer for a pad under test. This permits testing of continuity between the pad and the input buffer. An output buffer can also be tested as applicable. In another embodiment, two or more pads of a die are electronically coupled together such that leakage current testing applied by a probe connected to one pad can be used to test another pad.