Integrated Circuit Pad and ESD Protection Layer Stacking
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Solution Overview
Problem
The challenge is to reduce the size of display drivers in integrated circuit devices while maintaining their functionality, as shrinking the devices using microfabrication technology makes them difficult to mount due to increased pitch requirements and inefficient layout designs.
Innovation Solution
The solution involves an integrated circuit device with a pad and an electrostatic discharge protection element, where the pad is positioned above the protection element, allowing for a more efficient use of space and adjustment of current drive capability, thereby reducing the layout area and facilitating mounting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the integrated circuit device is shrunk by microfabrication technology, then the chip size is reduced, but it becomes difficult to mount the device due to insufficient output pitch
Solution Approach 1:
The electrostatic discharge protection element is positioned in the lower layer beneath the pad, utilizing the vertical dimension (layer stacking) rather than expanding the horizontal layout. This allows the output pitch to be determined by the pad width in the upper layer, while the protection element occupies space in the lower layer, thus reducing chip area without compromising mounting ease.
Solution Approach 2:
The electrostatic discharge protection element is nested beneath the pad structure, with the pad in the upper layer covering part or all of the protection element in the lower layer. This nested arrangement allows both elements to coexist in a compact footprint, maintaining the required output pitch for mounting while reducing overall chip size.
2Area of moving object
If the layout area is reduced, then chip size decreases, but the current drive capability may be compromised
Solution Approach 1:
The invention moves the electrostatic discharge protection element to the lower layer, freeing up horizontal layout space while maintaining adequate transistor dimensions for current drive capability. The vertical stacking allows the pad and protection element to share the same footprint without interfering with each other's electrical characteristics.
Solution Approach 2:
The invention allows independent optimization of the pad dimensions (which determine output pitch and mounting characteristics) and the electrostatic discharge protection element dimensions (which determine current drive capability). By separating their functional requirements and positioning them in different layers, both parameters can be optimized simultaneously.
Data Source
AI summary
An integrated circuit device includes a pad PDx and an electrostatic discharge protection element ESDx formed in a rectangular region and electrically connected with the pad PDx. The pad PDx is disposed in an upper layer of the electrostatic discharge protection element ESDx so that an arrangement direction of the pads is parallel to a long side direction of the region in which the electrostatic discharge protection element ESDx is formed, and the pad PDx overlaps part or the entirety of the electrostatic discharge protection element ESDx.