Integrated Circuit Pad Overlap for Chip Area Reduction
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Solution Overview
Problem
The challenge is to reduce the size of display drivers in integrated circuit devices while maintaining their functionality, as shrinking the devices using microfabrication technology leads to difficulties in mounting and increases costs due to increased glass frame size and unnecessary wiring regions.
Innovation Solution
The design incorporates first and second transistors connected by a charge-pump operation with an electrostatic discharge protection element and a pad connected to a flying capacitor, where the pad overlaps the transistors, allowing for reduced wiring efficiency and width, and the transistors are disposed under the pad to enhance electrostatic discharge resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the chip size is reduced by shrinking the integrated circuit device using microfabrication technology, then the device size decreases, but it becomes difficult to mount the device due to narrower pitches and increased glass frame sizes
Solution Approach 1:
The pad is disposed in an upper layer of the transistors and protection elements, allowing the pad to overlap part or the entirety of these components vertically. This three-dimensional stacking approach reduces the horizontal area occupied by the pad and associated wiring, enabling smaller chip size while maintaining mounting feasibility through optimized pitch dimensions
2Area of stationary object
If the pad is disposed in an upper layer overlapping transistors and protection elements, then the device width is reduced and wiring is minimized, but the electrostatic discharge protection capability must be maintained
Solution Approach 1:
The electrostatic discharge protection element is positioned beneath the pad in a vertical stacking arrangement, with the pad disposed in an upper layer overlapping the protection element. This nested configuration allows the protection element to be integrated within the same footprint as the pad, reducing overall device width while maintaining ESD protection functionality through the underlying protection structure
Solution Approach 2:
The pad structure serves as an intermediary element that connects to both the flying capacitor and the electrostatic discharge protection element below it. This intermediary positioning allows the pad to transmit signals while the underlying protection element provides ESD protection, resolving the conflict between minimized device width and maintained protection capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in a narrower integrated circuit device that facilitates easier mounting and reduces costs by minimizing the chip area while maintaining the necessary width for circuit blocks, allowing for efficient signal transmission and layout design.
Implementation Method 1
first and second transistors push-pull connected between first and second power supply lines and outputting a voltage of one of the first and second power supply lines to a connection node by a charge-pump operation
Implementation Method 2
an electrostatic discharge protection element connected between the first power supply line and the connection node
Data Source
AI summary
An integrated circuit device includes first and second transistors NTr1 and PTr1 push-pull connected between first and second power supply lines and outputting a voltage of one of the first and second power supply lines to a connection node ND by a charge-pump operation, and a pad PD electrically connected with the connection node ND and electrically connected with a flying capacitor, to which a given voltage is applied at one end, at the other end of the flying capacitor. The pad PD is disposed in an upper layer of at least one of the first and second transistors NTr1 and PTr1 so that the pad PD overlaps part or the entirety of at least one of the first and second transistors NTr1 and PTr1.