IC Pad Buffer Voltage Shifting for High-Voltage External Interfaces
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Solution Overview
Problem
Existing integrated circuit connection devices are limited in connecting external components with operating voltages higher than the integrated circuit supply voltage, leading to noise and excessive power consumption due to current injection and incompatibility with reducing circuit supply voltages.
Innovation Solution
Incorporating switching means to modify the voltage signal amplitude applied to the active transistors, allowing the integrated circuit to adapt its voltage range to external components, using selection and conversion means such as voltage comparators and level shifters to ensure the buffer remains non-conductive even when the external component's voltage exceeds the supply voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the integrated circuit uses a reduced supply voltage to reduce power consumption, then energy efficiency is improved, but the ability to connect external components with higher operating voltages is lost
Solution Approach 1:
The gate voltage of the PMOS transistor is made dynamic rather than fixed at the supply voltage. A control circuit adjusts the gate voltage level based on the operating voltage of the connected external component, allowing the buffer to remain non-conductive even when external component voltage exceeds the reduced supply voltage. This dynamic adjustment enables both reduced power consumption and voltage adaptability.
Solution Approach 2:
The invention changes the parameter of gate voltage level for the PMOS transistor from a fixed value (supply voltage) to an adjustable value. By modifying this parameter through the control circuit, the system can adapt to different external component voltage requirements while maintaining the buffer in a non-conductive state, thus preventing current injection and enabling reduced supply voltage operation.
2Object-generated harmful factors
If the buffer is kept non-conductive to prevent current injection and noise, then power consumption and noise are reduced, but the ability to interface with external components operating at different voltages is limited
Solution Approach 1:
The control circuit dynamically adjusts the gate voltage parameter of the PMOS transistor based on the external component's operating voltage. This parameter change allows the buffer to remain non-conductive (preventing current injection and noise) while simultaneously accommodating external components with different voltage levels, thus resolving the contradiction between noise reduction and voltage adaptability.
3Ease of operation
If the PMOS transistor gate voltage is kept at supply voltage level to ensure proper operation, then transistor control is simplified, but external components with higher operating voltages cannot be connected
Solution Approach 1:
A control circuit is introduced as an intermediary between the supply voltage and the PMOS transistor gate. This intermediary component manages the complexity of voltage level adaptation, automatically adjusting the gate voltage to appropriate levels based on external component requirements. This intermediary approach maintains ease of operation by automating the voltage adjustment process while enabling voltage compatibility with external components.
Data Source
AI summary
The integrated circuit connection device (1) enables an external component to be connected. The integrated circuit is powered by a supply voltage (VDD) and part of the circuit operates using at least one internal regulated voltage (VREG). The connection device includes two active transistors (N1, P1) of different conductivity connected in series between the supply voltage (VDD) and earth (VSS). The drains of these two active transistors (N1, P1) are connected to each other so as to form an external contact pad (2). The gates of these active transistors are controlled by voltage signals that have the same amplitude (Vesd). The connection device further includes switching means (3) for modifying the control signals (Vesd) applied across the active transistor gates, without exceeding the highest voltage between the supply voltage (VDD) and the internal regulated voltage (VREG). This allows the voltage range of said integrated circuit to be adapted to an external component connected to the external contact pad (2).