System-Level Parameter Estimation for IC Development
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Solution Overview
Problem
As integrated circuit complexity increases, development cycles lengthen due to uncertainties in interface requirements and integration of analog blocks, leading to delayed product introduction cycles and increased risk.
Innovation Solution
An integrated platform that includes an IP bank, application bank, and technology bank, utilizing a model generator to create a hierarchical table and perform estimations of performance, power, area, and cost (PPAC) for integrated circuits, allowing for early evaluation and removal of defective architectures, thereby expediting the development of mask sets for fabricating ICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If chip complexity increases to achieve higher performance, then performance is improved, but development cycle lengthens and risk increases
Solution Approach 1:
The patent performs PPAC estimation and architectural evaluation before final IC design completion. By conducting system-level simulations and analyses at the architecture level using virtual platforms, the methodology identifies potential issues early in the design process, allowing corrections to be made before committing to expensive physical implementation, thereby shortening the overall development cycle despite increased chip complexity.
2Power
If chip complexity increases to achieve higher performance, then performance is improved, but development risk increases
Solution Approach 1:
The patent performs PPAC estimation and architectural evaluation before final IC design completion. By conducting system-level simulations and analyses at the architecture level using virtual platforms, the methodology identifies potential issues early in the design process, allowing corrections to be made before committing to expensive physical implementation, thereby shortening the overall development cycle despite increased chip complexity.
3Measurement precision
If traditional estimation methods are used for each block separately, then detailed analysis is possible, but overall system evaluation is incomplete and time-consuming
Solution Approach 1:
The patent merges individual block-level PPAC estimates into a comprehensive system-level evaluation. The virtual platform integrates multiple IP blocks with defined interfaces and interactions, allowing simultaneous evaluation of the entire system's performance, power, area, and cost characteristics. This holistic approach maintains detailed analysis capabilities while reducing total evaluation time through coordinated system-level simulation.
Solution Approach 2:
The virtual platform serves multiple evaluation functions simultaneously - it can assess performance metrics, power consumption, area utilization, and cost implications across the entire IC architecture. This multi-functional evaluation system replaces multiple separate analysis tools and processes, providing comprehensive system-level insights without requiring sequential execution of individual block analyses.
Data Source
AI summary
A method is disclosed that includes providing an IP bank, an application bank, and a technology bank; generating a hierarchical table based on the IP bank and the application bank; performing an estimation of at least one of a performance value, a power value, an area value and a cost value, which corresponds to the hierarchical table, by using the technology bank, to output an result data as a basis of fabrication of a system.