Parametric Perturbations for IC Timing Analysis

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Solution Overview

Problem

Current methods for statistical timing analysis of digital circuits are inefficient due to the need for extensive corner-based analysis, which is inadequate for capturing intra-die and inter-die variations, especially when dealing with a large number of independent process variables, leading to excessive computational costs and inaccuracies.

Innovation Solution

A method for simulating parametric variations in integrated circuits by specifying an IC model, calculating perturbation values, and determining performance metrics, including voltage-sensitivity and performance-sensitivity values, using linear time-varying matrices and adjoint systems to efficiently analyze delays and waveform sensitivities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If corner-based methodology is used for timing analysis, then analysis coverage is improved, but analysis time increases excessively

Engineering Contradiction:
Improvetiming analysis accuracyVSAvoidanalysis time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent transforms the timing analysis approach from corner-based parameter evaluation to statistical parameter analysis. By modeling process variations as statistical distributions and using sensitivity analysis with respect to process parameters, the method achieves comprehensive coverage without enumerating all corner cases, thus reducing analysis time while maintaining reliability.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the mechanical corner-based analysis system with a statistical modeling system. Instead of systematically evaluating discrete corner cases, the invention uses statistical distributions to represent process variations and computes timing metrics through statistical methods, fundamentally changing the analysis mechanism.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If statistical timing analysis is implemented, then realism of timing analysis is improved, but computational complexity increases

Engineering Contradiction:
Improvetiming analysis realismVSAvoidcomputational complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the computational problem by separating the statistical modeling component from the timing analysis component. By pre-computing sensitivities with respect to process parameters and using these sensitivities to evaluate timing under statistical variations, the method reduces overall computational complexity while maintaining statistical realism.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary computation of sensitivity coefficients with respect to process parameters before conducting the statistical timing analysis. These pre-computed sensitivities are then reused to evaluate timing under various statistical conditions, avoiding redundant computations and reducing overall computational complexity.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If black-box techniques such as RSMs are applied, then analysis speed is improved, but applicability to large numbers of process variables deteriorates

Engineering Contradiction:
Improveanalysis speedVSAvoidhandling of process variables
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent changes the parameter representation from fixed RSM coefficients to sensitivity-based statistical models. By expressing timing metrics as functions of process parameter sensitivities and statistical moments, the method maintains analysis speed while becoming highly adaptable to systems with large numbers of process variables, including MOS parameter mismatch and interconnect variations.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8180621B2Parametric perturbations of performance metrics for integrated circuits
Publication Date: 2012.05.15 CADENCE DESIGN SYST INC
  • US8180621B2 patent drawing
  • US8180621B2 patent drawing
  • US8180621B2 patent drawing

AI summary

A method of simulating parametric variations in an integrated circuit (IC) includes: specifying an IC model, wherein the IC model includes one or more parameters for variation about a nominal condition; calculating parametric perturbations about the nominal condition; and saving one or more values for the parametric perturbations in a computer-readable medium. Calculating the parametric perturbations includes: simulating the nominal condition for the IC; determining perturbation values for the IC model about the nominal conditions, wherein the perturbation values include linear time-varying matrices and parametric right-hand sides, determining a performance metric for the IC and a performance sampling vector for sampling the performance metric about the nominal condition from the perturbation values; and determining voltage-sensitivity values and performance-sensitivity values from the perturbation values and the performance-sampling vector.