IC Partition Reset Circuit for Scan Mode Exit Optimization
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Solution Overview
Problem
The existing methods for testing integrated circuits (ICs) using automatic test equipment (ATE) require frequent power-on-reset or global reset to exit scan mode, which increases test time, degrades flash memory, and causes unnecessary programming of electronic fuses, and can result in accidental resets due to glitches.
Innovation Solution
A reset circuit that receives multiple signals to selectively reset specific partitions of the IC, using a counter to determine the type of reset, allowing for granular control of IC resets rather than full IC resets, thereby reducing test time and minimizing flash memory degradation and accidental resets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power-on-reset or global reset is performed to exit scan mode, then the IC is reset to a known state, but test time increases and flash memory degrades
Solution Approach 1:
The IC is divided into multiple partitions (first partition, second partition, etc.), and the reset function is segmented to allow selective resetting of individual partitions rather than the entire IC. The reset circuit receives partition reset signals that can independently control the reset state of each partition, enabling granular reset management that reduces unnecessary initialization operations and associated time losses.
Solution Approach 2:
Different partitions of the IC can be reset independently based on local requirements. When exiting scan mode, only the specific partition that needs resetting is affected, while other partitions maintain their operational state. This local quality approach prevents unnecessary global initialization and reduces test time.
2Reliability
If power-on-reset or global reset is performed to exit scan mode, then the IC is reset to a known state, but flash memory degradation increases
Solution Approach 1:
The reset function is segmented at the partition level, allowing the reset circuit to selectively reset only the necessary partition without triggering a full IC reset. This segmentation prevents unnecessary flash memory access and programming operations that would occur during global reset initialization, thereby reducing flash memory degradation.
Solution Approach 2:
Instead of performing a complete global reset that resets the entire IC, the system applies partial reset action only to the specific partition that requires it. This partial action approach minimizes the scope of initialization operations, reducing unnecessary flash memory programming and trimming operations.
3Reliability
If power-on-reset or global reset is performed to exit scan mode, then the IC is reset to a known state, but unnecessary programming of electronic fuses occurs
Solution Approach 1:
The reset operation is segmented to affect only the specific partition that needs resetting, rather than the entire IC. This prevents unnecessary programming operations on electronic fuses in partitions that do not require resetting, thereby reducing programming time and associated costs.
Solution Approach 2:
The reset circuit applies local reset quality to specific partitions based on their individual needs. When exiting scan mode, only the partition that requires resetting undergoes initialization including electronic fuse programming, while other partitions skip this time-consuming operation.
4Reliability
If global reset is performed to exit scan mode, then the IC is reset to a known state, but test time increases due to repeated initialization
Solution Approach 1:
The reset functionality is segmented to operate at the partition level rather than globally. This allows the testing process to maintain higher productivity by resetting only the necessary partition when exiting scan mode, avoiding repeated full IC initialization that slows down the testing cycle.
Solution Approach 2:
The system applies partial reset action only to the extent necessary (specific partition) rather than performing excessive global reset operations. This partial action approach maintains testing productivity by minimizing the time spent on initialization while still achieving the required reset state for reliable testing.
Data Source
AI summary
Resetting an integrated circuit (IC) by reset circuit of the IC comprises receiving a clock signal and a data signal. A sequence of bits of the data signal is stored in a memory based on the clock signal. A test mode signal is received and the sequence of bits is decoded in response to receiving the test mode signal. One of adjusting a counter value of a counter of the reset circuitry and outputting a reset signal corresponding to the counter value is performed based on the decoded sequence of bits.