IC Passivation Stack for Moisture Barrier Without Stress Cracking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing passivation layers in integrated circuit devices are prone to stress-induced cracking, allowing contaminants like moisture and protons to infiltrate and cause reliability failures such as temperature humidity bias (THB) and high temperature reverse bias (HTRB) failures.
Innovation Solution
A passivation layer comprising a stack of tetraethyl orthosilicate (TEOS), Phosphorus doped TEOS (PTEOS), and high-density Silicon-rich Nitride layers is used, with the TEOS and PTEOS extending over certain surface portions and the Silicon-rich Nitride providing a moisture-resistant barrier, while the TEOS layer acts as a stress-relieving and diffusion barrier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a passivation layer is used to protect integrated circuit devices, then reliability is improved, but stress-induced cracking occurs allowing contaminant infiltration
Solution Approach 1:
The passivation layer is divided into multiple functional layers: a low-stress TEOS layer (50-200 nm thick) that acts as a stress buffer, and a high-density Silicon-rich Nitride layer (200-500 nm thick) that provides the primary contaminant barrier. This segmentation allows each layer to perform its specialized function, preventing stress-induced cracking while maintaining reliability.
Solution Approach 2:
The patent employs a composite passivation structure combining TEOS (tetraethyl orthosilicate) and Silicon-rich Nitride materials. The TEOS layer provides stress relief properties, while the Silicon-rich Nitride layer provides superior moisture and proton barrier properties. This composite approach resolves the contradiction by combining materials with complementary properties.
2Object-affected harmful factors
If the passivation layer is made thicker to improve barrier properties, then contaminant resistance is improved, but stress-induced cracking increases
Solution Approach 1:
Instead of using a single thick passivation layer, the solution segments the barrier function into two layers with different thicknesses and functions. The TEOS layer (50-200 nm) absorbs stress, while the thinner Silicon-rich Nitride layer (200-500 nm) provides the contaminant barrier. This segmentation achieves effective protection without the stress problems of a single thick layer.
Solution Approach 2:
Different regions of the passivation structure have different properties optimized for their specific functions. The TEOS layer has low stress properties localized at the interface with the metal contact, while the Silicon-rich Nitride layer has high barrier properties localized at the exposed surfaces. This local quality optimization resolves the contradiction between thickness and stress resistance.
3Device complexity
If a single-layer passivation structure is used, then device complexity is reduced, but barrier effectiveness against moisture and protons is insufficient
Solution Approach 1:
The patent uses a composite two-layer passivation structure where TEOS provides stress management and Silicon-rich Nitride provides superior moisture and proton barrier properties. This composite approach achieves effective contaminant protection while maintaining relatively simple fabrication processes, resolving the contradiction between complexity and barrier effectiveness.
Solution Approach 2:
The passivation structure performs multiple functions simultaneously: the TEOS layer provides stress relief and adhesion, while the Silicon-rich Nitride layer provides contaminant barrier protection. This multi-functionality achieves comprehensive protection without requiring additional separate structures, balancing complexity and effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed passivation layer effectively inhibits contaminant intrusion, enhancing the reliability of integrated circuit devices by providing a robust barrier against moisture and proton penetration, thereby reducing the risk of THB and HTRB failures.
Implementation Method 1
the TEOS layer acts as a stress-relieving and diffusion barrier
Implementation Method 2
the TEOS layer acts as a stress-relieving and diffusion barrier
Implementation Method 3
the high-density Silicon-rich Nitride providing a moisture-resistant barrier
Data Source
AI summary
An integrated circuit device includes a metal contact and a passivation layer extending on a sidewall of the metal contact and on first and second surface portions of a top surface of the metal contact. The passivation layer is format by a stack of layers including: a tetraethyl orthosilicate (TEOS) layer; a Phosphorus doped TEOS (PTEOS) layer on top of the TEOS layer; and a Silicon-rich Nitride layer on top of the PTEOS layer. The TEOS and PTEOS layers extend over the first surface portion, but not the second surface portion, of the top surface of the metal contact. The Silicon-rich Nitride layer extends over both the first and second surface portions, and is in contact with the second surface portion.