Integrated Circuit Path Tracing for Faster Static Timing Analysis
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for verifying integrated circuits, particularly dynamic random access memory (DRAM), face challenges due to the impossibility of block-level static timing analysis and long runtime of static timing analysis (STA) due to circuit complexity, making it difficult to simulate all cases and create design constraints efficiently.
Innovation Solution
A method and system for performing static timing analysis (STA) on specified paths within integrated circuits, involving tracing and generating design constraints and parasitic data for these paths, reducing the verification time by focusing on specific paths rather than the entire circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If static timing analysis is performed on the entire integrated circuit, then timing verification completeness is improved, but verification time and turnaround time increase significantly
Solution Approach 1:
The patent divides the entire integrated circuit into multiple specified paths for separate timing analysis. The tracing module extracts and identifies specific signal transfer paths from the transistor-level netlist, allowing static timing analysis to be performed on individual paths rather than the entire circuit at once. This segmentation maintains timing verification completeness for critical paths while significantly reducing overall verification time.
Solution Approach 2:
The patent extracts only the necessary specified paths from the complete circuit netlist using the tracing module. By identifying and extracting specific signal transfer paths that need timing verification, the system performs analysis only on relevant portions of the circuit, eliminating unnecessary analysis of unrelated circuit portions while maintaining verification completeness for critical timing paths.
2Reliability
If static timing analysis is performed on the entire integrated circuit, then timing verification completeness is improved, but device complexity and difficulty of creating design constraints increase
Solution Approach 1:
The patent segments the complex integrated circuit into manageable specified paths, each of which can be analyzed independently. The tracing module breaks down the transistor-level netlist into discrete signal transfer paths, making it feasible to create and manage design constraints for individual paths rather than attempting to constrain the entire complex circuit at once.
Solution Approach 2:
The patent extracts only the essential specified paths from the complex circuit structure. By focusing analysis on extracted specific paths rather than the complete circuit, the system reduces the complexity of creating design constraints while maintaining timing verification completeness for the extracted paths.
3Adaptability or versatility
If dynamic timing analysis is used for verification, then all signal transfer paths can be simulated, but it is impossible to simulate all cases that may occur within the circuit
Solution Approach 1:
The patent segments the circuit analysis into specific identified paths using the tracing module. By extracting and analyzing each specified path individually, the system can systematically cover all possible signal transfer scenarios that would be difficult to achieve through dynamic timing analysis, while maintaining adaptability to different verification scenarios.
Solution Approach 2:
The patent performs preliminary tracing to identify and extract all specified paths before conducting timing analysis. This preliminary action of path identification ensures that all possible signal transfer cases are captured in advance, enabling comprehensive verification coverage without relying on dynamic simulation of all cases during operation.
Data Source
AI summary
A system for verifying an integrated circuit includes a tracing module configured to: trace a specified path based on the specified path on which a timing analysis will be performed among a plurality of signal transfer paths within the integrated circuit and a netlist of the integrated circuit at a transistor level, generate a list of nets listing names of nets in the specified path based on the netlist and information on the specified path, declare design constraints for the specified path based on the list of the nets, and generate parasitic data for the net based on the list of the nets. The system further includes an analysis module configured to perform a timing analysis for the specified path based on the design constraints and the parasitic data.