IC Pattern Clustering Using Simulation-Guided Representative Verification
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Solution Overview
Problem
Conventional methods fail to accurately reflect the physical properties and defect characteristics of integrated circuit patterns, leading to poor analysis and verification accuracy.
Innovation Solution
A method is provided for systematically verifying integrated circuits by generating clustering that reflects physical properties and defect possibilities, involving pattern clustering based on geometric features, simulation results, and data sampling to balance similarities, with a feedback process to update clustering and select representative patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If patterns are clustered using only geometric features, then the clustering process is simple and fast, but the accuracy of reflecting physical properties and defect characteristics is poor
Solution Approach 1:
The patent combines multiple clustering approaches (geometric feature-based clustering and simulation result-based clustering) into a unified framework. The geometric clustering groups patterns by shape characteristics, while simulation-based clustering groups them by physical property responses. These clustering results are then integrated to achieve comprehensive pattern analysis that reflects both geometric and physical characteristics, thereby improving measurement precision without excessive complexity increase.
Solution Approach 2:
The patent introduces simulation results as an intermediary element that bridges geometric features and physical properties. Instead of directly analyzing complex physical behaviors, the simulation results serve as a mediator that captures essential physical characteristics (such as electromagnetic field distributions, thermal responses, or mechanical stresses) and feeds them back into the clustering process, enabling accurate reflection of physical properties while maintaining manageable complexity.
2Reliability
If all patterns are analyzed and verified individually, then comprehensive verification is achieved, but the development period is extended and efficiency is reduced
Solution Approach 1:
The patent segments the vast number of patterns into distinct clusters based on geometric features and simulation results. By grouping similar patterns together, the verification process can focus on representative patterns from each cluster rather than analyzing every single pattern individually. This segmentation maintains comprehensive verification coverage while dramatically improving productivity by reducing the number of detailed analyses required.
Solution Approach 2:
The patent applies partial action by performing comprehensive verification on a selected subset of representative patterns rather than all patterns. The clustering identification selects key representative patterns that capture the essential characteristics of each cluster, and verification efforts are concentrated on these partial cases. This approach achieves sufficient reliability for the integrated circuit while avoiding the excessive time cost of analyzing every pattern in detail.
3Measurement precision
If representative patterns are selected based only on geometric similarity, then selection is straightforward, but the representativeness regarding physical properties is insufficient
Solution Approach 1:
The patent implements feedback by using simulation results to inform and refine the representative pattern selection process. Simulation results regarding physical properties (such as electromagnetic characteristics, thermal behavior, or mechanical responses) are fed back into the selection criteria. This feedback mechanism ensures that selected representative patterns not only share geometric similarity but also exhibit comparable physical property behaviors, thereby improving representativeness while the automated feedback loop maintains ease of operation.
Data Source
AI summary
Provided is a method of evaluating an integrated circuit. The method includes obtaining a plurality of patterns representing a layout of the integrated circuit; clustering the plurality of patterns into a plurality of clusters based on geometric features of the plurality of patterns, and simulation results obtained by simulating properties of the plurality of patterns; selecting a representative pattern of each of at least one cluster of the plurality of clusters; and verifying the representative pattern of each of at least one cluster and evaluating performance of the integrated circuit based on this.