IC Pattern Density Optimization via Local Dummy Shape Insertion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current integrated chip (IC) design processes face challenges in maintaining optimal pattern density, leading to processing failures and defects during chemical mechanical polishing due to low-pattern-density areas, which require extensive optical proximity correction (OPC) cycles and resource consumption.
Innovation Solution
The method involves identifying low-pattern-density areas within an IC design and adding dummy shapes locally to adjust the pattern density, reducing the scope of subsequent data preparation processes like OPC, thereby minimizing resource demands and cycle time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy shapes are added throughout the entire IC design to improve pattern density, then pattern density control is improved, but OPC cycle time and resource consumption increase significantly
Solution Approach 1:
The patent applies local quality by identifying specific low-pattern-density areas within the IC design and adding dummy shapes only in those localized regions rather than throughout the entire design. This targeted approach maintains pattern density control where needed while minimizing the number of dummy shapes subjected to OPC, thereby reducing OPC cycle time and resource consumption.
Solution Approach 2:
The patent segments the IC design into regions with adequate pattern density and regions with low pattern density. By applying dummy shape insertion only to the low-density segments, the solution divides the problem into manageable parts, reducing the overall scope of OPC operations while maintaining pattern density control in critical areas.
2Manufacturing precision
If dummy shapes are added throughout the entire IC design to improve pattern density, then pattern density control is improved, but computational resources and processing power are consumed excessively
Solution Approach 1:
The patent reduces computational resource consumption by applying dummy shape insertion only to locally identified low-pattern-density areas rather than the entire IC design. This localized approach maintains pattern density control where problematic while significantly reducing the computational burden of subsequent OPC operations on fewer dummy shapes.
3Manufacturing precision
If dummy shapes are added to low-pattern-density areas to prevent CMP dishing, then substrate planarity is improved, but the complexity of the design increases
Solution Approach 1:
The patent reduces design complexity by adding dummy shapes only in specific low-pattern-density areas identified through analysis, rather than uniformly throughout the entire design. This localized approach prevents CMP dishing in critical areas while minimizing the overall increase in design complexity and the number of dummy shapes that require documentation and processing.
Data Source
AI summary
The present disclosure relates to a method of data preparation. The method, in some embodiments, performs a first data preparation process using a data preparation element. The first data preparation process modifies a plurality of shapes of an integrated chip (IC) design that comprises a graphical representation of a layout used to fabricate an integrated chip. A plurality of additional shapes are added to the IC design using an additional shape insertion element. The plurality of additional shapes are separated from the plurality of shapes by one or more non-zero distances. A second data preparation process is performed using the data preparation element, after performing the first data preparation process. The second data preparation process modifies the plurality of additional shapes.