Integrated Circuit Pattern Evaluation for Weak Point Detection

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Solution Overview

Problem

Integrated circuits manufactured through semiconductor processes often deviate from design layout due to miniaturization and process variations, leading to shape discrepancies that can result in weak points, reducing performance and reliability.

Innovation Solution

A computing system evaluates integrated circuit patterns by extracting and superimposing design patterns with common shapes from input layout data, generating distribution data, determining evaluation contours, and replacing patterns to identify and mitigate weak points, thereby improving the integration of circuits into semiconductor devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If semiconductor process miniaturization is pursued to increase circuit density, then more elements can be integrated, but manufacturing precision deteriorates causing shape deviations from design layout

Engineering Contradiction:
Improvenumber of elementsVSAvoidshape conformity
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by performing statistical analysis and contour determination on inspected patterns before final device fabrication. The system evaluates distribution data of inspected patterns and determines evaluation contours in advance to identify and filter out weak points, preventing defective circuits from proceeding to fabrication. This proactive evaluation approach addresses the manufacturing precision deterioration caused by miniaturization by preparing compensation strategies before production.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If inspection of integrated circuit patterns is performed to evaluate weak points, then reliability can be assessed, but measurement precision requirements increase due to shape discrepancies

Engineering Contradiction:
Improvecircuit reliabilityVSAvoidpattern measurement accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent applies parameter changes by transforming the evaluation approach from measuring individual pattern dimensions to analyzing statistical distribution parameters. Instead of requiring high-precision measurement of each pattern's exact shape, the system collects inspection data and analyzes distribution characteristics (mean, standard deviation) of pattern shapes. This statistical parameter transformation enables reliable reliability assessment while accommodating the measurement precision limitations introduced by miniaturization and process variations.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If design layout data is used to manufacture integrated circuits, then manufacturing process is simplified, but shape deviations occur due to process variations

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidpattern shape accuracy
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent implements feedback by establishing a closed-loop system that inspects manufactured patterns, analyzes distribution data, determines evaluation contours, and feeds this information back to identify and filter weak points. The inspection results are used to evaluate whether circuits meet reliability thresholds before fabrication, creating a feedback mechanism that compensates for process variations without complicating the manufacturing process itself. This feedback loop maintains ease of manufacture while addressing shape deviations through post-manufacturing evaluation and selection.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10885261B2Systems and methods of fabricating semiconductor devices
Publication Date: 2021.01.05 SAMSUNG ELECTRONICS CO LTD
  • US10885261B2 patent drawing
  • US10885261B2 patent drawing
  • US10885261B2 patent drawing

AI summary

Patterns in an integrated circuit may be evaluated, and a semiconductor device may be fabricated based on the evaluation. The evaluation may include a extracting and superimposing first patterns corresponding to design patterns of the same shape from input layout data generated based on inspecting the integrated circuit, generating distribution data of the first patterns based on the superimposed first patterns, determining an evaluation contour of the design patterns based on an evaluation condition and the distribution data, and generating output layout data based on replacing the first patterns with second patterns each having the evaluation contour. Weak points in the integrated circuit may be detected based on the output layout data. The fabricating may include selectively incorporating an integrated circuit into a semiconductor device based on a determination that the integrated circuit includes less than a threshold quantity and/or threshold concentration of weak points.