Integrated Circuit Performance Binning via Hardware Monitors
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Solution Overview
Problem
Conventional methods for testing and determining the performance of integrated circuits are costly and time-consuming, particularly when correlating actual speed with numerous functional/AC scan patterns and critical paths, making them inefficient for large-scale chip verification.
Innovation Solution
Incorporating Hardware Performance Monitors (HPMs) into integrated circuits, along with a built-in self-test (BIST) module and storage unit, to generate performance values and weights, enabling the determination of chip performance through a performance function and automatic binning, which reduces the need for extensive post-silicon testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional functional/AC scan patterns are used to test integrated circuit performance, then measurement precision is improved, but loss of time and productivity deteriorate due to costly and time-consuming correlation processes
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing performance binning weights in a lookup table during design time. This allows the testing system to directly query pre-computed performance bins based on measured delay values, eliminating the need for time-consuming post-silicon correlation analysis between thousands of critical paths and actual performance data.
Solution Approach 2:
The patent uses copying by creating a simplified model of the performance correlation through pre-computed weights that represent the relationship between critical path delays and actual circuit performance. Instead of performing complex correlation analysis on actual chips, the system copies the essential correlation information into lookup tables that can be quickly queried during testing.
2Measurement precision
If thousands of critical paths are observed to determine chip performance, then measurement precision is improved, but device complexity and loss of time worsen due to the large number of paths to analyze
Solution Approach 1:
The patent extracts the essential performance correlation information from the complex system of thousands of critical paths by computing and storing weights that represent the aggregated impact of path delays. This extraction process separates the complex correlation analysis from the actual testing operation, leaving only simple weight-based binning queries during chip testing.
Solution Approach 2:
The patent employs cheap short-living objects by using pre-computed weight tables that can be rapidly queried and discarded. Instead of maintaining complex, long-lived correlation analysis systems, the invention uses lightweight lookup tables that provide sufficient precision for binning purposes without the overhead of complex ongoing analysis.
3Measurement precision
If conventional post-silicon correlation methods are used, then measurement precision is improved, but productivity and loss of time deteriorate due to the extensive analysis required
Solution Approach 1:
The patent applies preliminary action by performing all complex correlation analysis and weight computation during the design and manufacturing preparation phase. This preliminary work produces lookup tables that enable rapid binning decisions during actual chip testing, dramatically improving productivity while maintaining precision through the pre-computed correlation data.
Data Source
AI summary
A method for determining performance of an integrated circuit (IC) is disclosed herein. The method includes following operations: disposing hardware performance monitors (HPMs) in each of ICs, in which each of HPMs generates a value for generating the performance of the IC; providing a performance function including of terms according to values generated by the HPMs, in which a weight is associated with each of terms; determining the weight of each of terms according to a first set of ICs of the ICs, wherein the performance of each of the ICs is known; and determining the performance of a first ICs of the ICs according to the performance function, wherein the performance function and the weights are built into the first ICs.