Integrated Circuit Physical Synthesis Timing Accuracy
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Solution Overview
Problem
In the design of integrated circuits, the separation of synthesis and placement processes leads to inaccuracies in timing predictability due to significant interconnect delays, causing post-synthesis and post-layout results to often fail in meeting design criteria, necessitating repeated iterations through the synthesis and placement/routing processes.
Innovation Solution
An iterative process that combines synthesis and placement transforms, allowing incremental changes and updates based on current design metrics such as timing, resource availability, and power, with placement occurring before resource type identification, and using transforms like high-level optimization and refinement to improve circuit performance and resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If synthesis and placement processes are separated, then the design process is simpler and more modular, but timing predictability deteriorates due to significant interconnect delays
Solution Approach 1:
The patent merges the synthesis and placement processes into a unified physical synthesis flow. The placement information is fed back into the synthesis process, allowing synthesis to occur with actual physical placement data rather than statistical estimates. This integration enables accurate timing prediction by considering real interconnect delays from the placement stage during synthesis optimization.
2Productivity
If statistical models are used for interconnect delay estimation, then the synthesis process is faster, but the accuracy of timing estimation deteriorates
Solution Approach 1:
The patent performs placement before synthesis in a reversed flow, obtaining actual placement information and interconnect delay data before the synthesis process begins. This preliminary action provides accurate physical placement data and real interconnect delay measurements that are then used during synthesis to make accurate timing predictions without requiring multiple iterative passes.
3Ease of manufacture
If placement is performed after synthesis, then the netlist is fully optimized, but the placement cannot account for timing constraints accurately due to lack of physical context
Solution Approach 1:
The patent inverts the traditional flow by performing placement before synthesis. This inversion allows the synthesis process to occur with knowledge of the actual physical placement and interconnect delays, enabling timing-driven optimization during synthesis rather than after placement. The netlist is optimized with accurate timing context from the beginning.
4Measurement precision
If multiple iterations through synthesis and placement are performed, then timing accuracy improves, but design productivity deteriorates
Solution Approach 1:
By performing placement before synthesis and obtaining actual interconnect delay data in advance, the patent eliminates the need for multiple iterative passes between synthesis and placement. The preliminary placement information provides accurate timing context that enables single-pass synthesis with high timing accuracy, dramatically improving design efficiency.
Data Source
AI summary
The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, a method of designing an integrated circuit comprises determining a state of a design of the integrated circuit at a high level design representation of the integrated circuit, wherein the state of the design of the integrated circuit comprises a netlist with at least one of timing data, resource information, placement information, routing information, and power data. The method further comprises determining a first transform for the state, changing the state of the design at the high level design representation of the integrated circuit using the first transform, and determining a second transform based on the changed state.