Integrated Circuit Pin Layout for Higher Access and Lower Routing Congestion
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Solution Overview
Problem
The increasing complexity and miniaturization of integrated circuits lead to routing congestion and signal delays due to limited pin access points, which affect performance and efficiency.
Innovation Solution
The integrated circuit design includes strategically placing lower and upper patterns with optimized spacing and via connections to increase pin access points, allowing for improved routing and reduced congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of devices in an integrated circuit is increased, then the integration density is improved, but routing congestion increases
Solution Approach 1:
The patent introduces multiple wiring layers (first wiring layer, second wiring layer, third wiring layer) to route signals in three-dimensional space rather than confined to a single plane. This dimensional expansion allows signals to bypass congested areas by routing through different layers, effectively increasing routing capacity without adding more devices to the same footprint area.
Solution Approach 2:
The patent divides the routing space into multiple discrete wiring layers, each with its own set of tracks and routing resources. By segmenting the routing problem across layers, the patent enables independent optimization of each layer's routing paths, reducing overall congestion while maintaining high device integration density.
2Area of moving object
If devices are miniaturized, then the device size is reduced, but pin access points become limited
Solution Approach 1:
The patent compensates for reduced pin access points in miniaturized devices by enabling routing in multiple dimensions through stacked wiring layers. Signals can access devices from different vertical levels, effectively increasing the number of accessible pin points without increasing the device's planar footprint area.
Solution Approach 2:
The patent creates a multi-functional wiring infrastructure where the same wiring layer structure serves multiple purposes: providing pin access points, enabling inter-device communication, and offering alternative routing paths. This universal wiring system maximizes the utility of limited pin access points in miniaturized devices.
3Adaptability or versatility
If wiring patterns are extended to increase pin access points, then routing flexibility is improved, but wiring layer complexity increases
Solution Approach 1:
The patent applies different routing strategies to different local regions of the integrated circuit. Each wiring layer can have locally optimized track assignments and routing patterns tailored to the specific density and connectivity requirements of that region, allowing routing flexibility to be improved without uniformly increasing complexity across the entire device.
Solution Approach 2:
The patent segments the wiring structure into multiple manageable layers with distinct routing functions. This segmentation allows each layer's complexity to be controlled independently, enabling overall routing flexibility through the combination of simpler, specialized layers rather than requiring a single complex unified wiring system.
Data Source
AI summary
An integrated circuit includes a first cell including a first lower pattern extending in a first direction along a first track in a first wiring layer; and a second cell including a second lower pattern that extends in the first direction along the first track in the first wiring layer, and is a minimum space of the first wiring layer or farther apart from the first lower pattern, wherein the first lower pattern corresponds to a pin of the first cell, and the second lower pattern is farther apart from a boundary between the first cell and the second cell than the first lower pattern is.