IC Pin Reconfiguration for Concurrent Testing
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Solution Overview
Problem
Design for testing (DFT) in integrated circuits (ICs) with lower pin counts poses challenges due to limited pin availability, requiring complex internal structures to support different signal communications during testing and nominal operations, often lacking dedicated test pins.
Innovation Solution
The integration of a plurality of testing circuits within ICs, each configured to sample internal data states and concurrently couple unique output signals to a shared pin, eliminating the need for dedicated test pins by utilizing existing pins for dual functionality, such as the GND pin for testing purposes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated test pins are used for testing, then testing capability is improved, but pin count increases
Solution Approach 1:
The patent applies multi-functionality by enabling existing pins to serve dual purposes: normal signal I/O during operational mode and test signal I/O during testing mode. The pin assignment circuit dynamically reconfigures pin functions based on mode, allowing the same physical pin to handle both operational and testing signals without requiring additional dedicated test pins.
2Quantity of substance
If pins are shared for different functions, then pin count is reduced, but internal structure complexity increases
Solution Approach 1:
The patent introduces a pin assignment circuit as an intermediary component that manages the switching between operational and testing modes. This mediator circuit receives mode selection signals and automatically configures the appropriate pin assignments, thereby managing the complexity of shared pin usage without requiring complex manual switching mechanisms throughout the entire IC structure.
3Adaptability or versatility
If mode switching circuitry is added for pin reconfiguration, then pin versatility is improved, but device complexity increases
Solution Approach 1:
The patent implements preliminary action by pre-configuring multiple pin assignment patterns within the pin assignment circuit. These patterns are prepared in advance for different operational modes (e.g., first mode, second mode, testing mode), and the circuit quickly switches between pre-defined configurations based on mode selection signals, avoiding the need for complex real-time reconfiguration logic.
Data Source
AI summary
An integrated circuit, comprising a plurality of pins, including a signal output pin. The integrated circuit also comprises a plurality of signal nodes. Each node in the plurality of signal nodes is operable to store a respective internal data signal. The integrated circuit also comprises a plurality of testing circuits. Each testing circuit in the plurality of testing circuits configured to sample a respective internal data state and in response to concurrently couple a unique output signal to a same pin in the plurality of pins, other than the signal output pin.