IC Pin-Sharing for SPI and I2C Multiprotocol Interfaces
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Solution Overview
Problem
Integrated circuit (IC) devices with multiprotocol communication interfaces face challenges in reducing the number of pins required for SPI and I2C interfaces, especially as die size decreases and available pinouts become limited.
Innovation Solution
The implementation of an efficient pin-sharing scheme between SPI and I2C interfaces in IC devices, where the I2C clock and data signals share the SPI clock and data pins, respectively, without the need for an additional dedicated selection pin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SPI and I2C interfaces use separate dedicated pins, then communication reliability is improved, but the number of pins required increases
Solution Approach 1:
The patent merges the clock and data signal lines of SPI and I2C interfaces by using tri-state buffers to enable both protocols to share the same physical pins. The tri-state buffers allow the shared pins to be dynamically assigned to either SPI or I2C based on the active protocol, reducing the total pin count while maintaining reliable communication for both protocols
Solution Approach 2:
The patent implements multi-functionality by designing the communication interface pins to serve dual purposes - they can function as SPI clock/data pins or I2C clock/data pins depending on the active protocol. This universal pin design allows the same physical pins to support multiple communication protocols, reducing the overall number of pins required
2Quantity of substance
If pins are shared between SPI and I2C, then the number of pins is reduced, but false mode switch detections increase
Solution Approach 1:
The patent applies preliminary action by implementing a debouncing mechanism that requires a threshold number of consecutive matching patterns before confirming a mode switch. This preliminary verification step prevents false mode switch detections by ensuring that the detected pattern is genuine and not caused by transient noise or interference
Solution Approach 2:
The patent implements feedback through a mode detection mechanism that continuously monitors the communication signals and compares them against expected patterns. The system provides feedback by counting consecutive matching patterns and only triggering a mode switch when the count exceeds a predefined threshold, thereby reducing false detections
3Reliability
If a dedicated selection pin is added for protocol switching, then mode switching reliability is improved, but the number of pins increases
Solution Approach 1:
The patent uses the existing CS pin universally for both SPI chip select functionality and I2C/SPI mode selection. By detecting specific patterns on this multi-functional pin, the system determines the active protocol without requiring an additional dedicated selection pin, thereby maintaining reliability while avoiding an increase in pin count
Data Source
AI summary
Systems and methods related to communication interface are provided. An interface circuitry arrangement for communication between integrated circuit (IC) devices, the interface circuitry arrangement including serial peripheral interface (SPI) circuitry having an SPI clock port, an SPI data port, and an SPI chip select (CS) port; inter-integrated circuit (I2C) circuitry having an I2C clock port and an I2C data port, wherein the I2C clock port and the SPI clock port are electrically coupled to a first connection port, and wherein the I2C data port and the SPI data port are electrically coupled to a second connection port; pattern detection circuitry to detect a signal pattern at a third connection port, the third connection port electrically coupled to the SPI CS port; and selection circuitry to selectively couple the SPI circuitry or the I2C circuitry to a data path responsive to an output of the pattern detection circuitry.