Analytical Placement Algorithm for IC Routability Optimization
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Solution Overview
Problem
Existing analytical global placement algorithms for integrated circuits do not optimize post-legalization routability, as they fail to consider preplaced blocks, white space, and legalization constraints effectively, leading to suboptimal placement plans with potential routing congestion and inadequate buffer space.
Innovation Solution
A method using a weighted objective function that balances wirelength and bin density terms to generate a global placement plan, involving clustering, declusterization, and iterative optimization to maximize routability, while ensuring sufficient unoccupied space and legal positioning of cell instances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If analytical placement algorithms position cells to optimize routability by reducing wirelength, then net length decreases, but cells may be placed in illegal positions causing overlap and requiring subsequent legalization
Solution Approach 1:
The patent applies preliminary action by performing look-ahead legalization during the global placement phase itself, rather than waiting for a separate legalization step. The algorithm anticipates future legalization requirements by incorporating legalization constraints into the placement optimization, pre-adjusting cell positions to account for upcoming legal positioning needs. This resolves the contradiction by proactively addressing placement legality while optimizing wirelength.
2Object-generated harmful factors
If placement algorithms distribute cells to provide routing space, then routing congestion decreases, but wirelength increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the weighting between wirelength minimization and congestion avoidance in the objective function during different phases of the placement algorithm. In early iterations, greater emphasis is placed on wirelength optimization, while in later iterations, congestion avoidance becomes more prominent. This time-varying parameter adjustment resolves the contradiction by balancing both competing requirements at different stages of the optimization process.
3Productivity
If global placement plans are generated without considering legalization constraints, then optimization speed increases, but additional legalization processing time is required
Solution Approach 1:
The patent applies preliminary action by integrating legalization constraint consideration directly into the global placement optimization process. Rather than generating placement plans without legalization constraints and then separately legalizing them, the algorithm incorporates legalization awareness from the beginning, performing look-ahead legalization that anticipates and prepares for legal positioning requirements during the main placement phase. This eliminates or reduces the need for separate legalization processing, resolving the time trade-off.
4Length of moving object
If placement algorithms focus on minimizing wirelength, then routing efficiency improves, but white space distribution becomes inadequate for buffer placement
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the objective function weights to shift emphasis from wirelength minimization to white space preservation during different phases of the algorithm. In later iterations, when wirelength optimization has converged, the algorithm increases the weight on congestion and white space metrics, ensuring adequate space for buffers and routing. This time-varying parameter adjustment resolves the contradiction by addressing both wirelength and white space requirements at appropriate stages.
Data Source
AI summary
A placer produces a global placement plan specifying positions of cell instances to be interconnected by nets within an integrated circuit (IC) by initially clusterizing cell instances to form a pyramidal hierarchy of blocks and generating an initial global placement plan specifying a position of each block at a highest level of the hierarchy. The placer then declusterizes the global placement plan by replacing the highest level blocks with their component blocks and then improves the routability of the global placement plan by iteratively moving specified block positions in directions and by distances dynamically determined by analyzing the global placement plan and an objective function having a total wirelength term and having a bin density term reflecting density of blocks in specified areas (bins) of the IC. The placer iteratively repeats the declusterization and routability improvement process until the global placement plan specifies positions of all blocks residing at the lowest level of the hierarchy, with weighting of the bin density term adjusted when necessary during each iteration of the routability improvement process to provide sufficient white space in each bin. The placer employs a look-ahead legalization technique to move low level blocks to legal positions during later iterations of the plan improvement process.