IC Placement-Routing Layout for Timing-Convergent Optimization

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The existing placement and routing methods in integrated circuit design suffer from a lack of correlation between the estimated routing resources in the placement stage and the actual resources required in the routing stage, leading to mismatches in timing, power, and area, resulting in poor circuit design quality.

Innovation Solution

A simultaneous placement and routing method that involves classifying constraint files, performing iterative verification and adjustment, and refining the grid to ensure that placement and routing are synchronized, using a core constraint file to determine actual routing resources and wire lengths, and adjusting illegal modules or sub-modules until timing convergence is achieved.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If placement and routing are performed as separate steps with estimated routing resources in the placement stage, then the placement process can be completed, but there is a mismatch between estimated and actual routing resources leading to poor design quality

Engineering Contradiction:
Improveplacement precisionVSAvoidrouting resource correlation
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent merges placement and routing into a single integrated process called simultaneous placement and routing (SPR). Instead of performing placement first with estimated routing resources and then routing separately, the invention performs both operations concurrently using a unified cost function that incorporates actual routing resource consumption. This eliminates the mismatch between estimated and actual routing resources that plagues separate-step approaches.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The invention implements feedback mechanisms where routing resource consumption information is continuously fed back to the placement process. The cost function includes terms that reflect actual routing resource usage, allowing the placement to be adjusted in real-time based on actual routing conditions rather than estimates. This feedback loop ensures that placement decisions are made with accurate knowledge of routing resource requirements.

Inventive Principle:
Principle #23Feedback

2Productivity

If fast pre-routing is performed during placement with real-time cost value calculation, then placement speed is improved, but the calculation complexity and operational speed difficulties increase significantly

Engineering Contradiction:
Improveplacement speedVSAvoidcalculation complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the simultaneous placement and routing process into manageable computational components. The cost function is divided into multiple terms (placement cost, routing cost, congestion cost, etc.) that can be calculated and updated independently. The grid-based approach segments the design space into discrete units, allowing efficient computation of routing resources. This segmentation reduces overall calculation complexity while maintaining placement speed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention changes the parameter representation from continuous to discrete grid-based values, making calculations more efficient. Routing resources are represented as discrete grid cells with integer values, allowing for faster computation compared to continuous representations. The cost function parameters are updated incrementally rather than recalculated from scratch, significantly reducing computational complexity while maintaining accuracy.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If the grid is refined and modules are divided into sub-modules for more precise placement, then placement precision is improved, but the computational complexity and processing time increase

Engineering Contradiction:
Improveplacement precisionVSAvoidprocessing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent uses grid segmentation where the design space is divided into discrete grid cells. The grid can be refined to appropriate levels based on design requirements without necessarily subdividing all modules. This selective segmentation allows achieving necessary precision while avoiding the exponential increase in computational complexity that would result from uniformly subdividing all modules.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention applies partial refinement where only certain regions or modules that require higher precision are subjected to finer grid resolution. Not all modules need to be divided into sub-modules - only those where precision is critical. This partial action approach achieves necessary precision for critical areas while maintaining faster processing for less critical areas, balancing precision and processing time.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS12547813B2Simultaneous placement and routing based method and apparatus for incremental design optimization, and computer device
Publication Date: 2026.02.10 ZHENGXINYUAN TECH (HANGZHOU) CO LTD
  • US12547813B2 patent drawing
  • US12547813B2 patent drawing
  • US12547813B2 patent drawing

AI summary

A simultaneous placement and routing based method and apparatus for incremental design optimization, and a computer device. The method includes according to a net-list file and a core constraint file acquired after logic synthesis, sequentially placing modules, each including units, on an initial coarse grid and simultaneously performing routing of each module and a placed module; performing iterative verification on placement and routing of the modules, and adjusting an illegal module and simultaneously adjusting routing of the illegal module according to a verification result, until requirements of the core constraint file are met; refining the grid, dividing each module into a plurality of sub-modules, and performing simultaneous placement and routing on the sub-modules in a refined grid; performing iterative verification and simultaneously adjusting placement and routing of illegal sub-modules; and repeating the above steps, until the iterative verification meets the requirements of the core constraint file and timing convergence.