IC Placement Control via State Bounds File

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Solution Overview

Problem

Conventional integrated circuit design methods face challenges in controlling physical placement, leading to variability and reduced quality of results due to insufficient macro and port placement controls, especially when dealing with complex designs and technology changes.

Innovation Solution

The placement director (PD) technique uses automatically derived state group bounds to reduce the placement search space, improve fluidity, and maintain placement quality by grouping similar state points and generating precise location bounds, allowing for refined control and reduced variance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional placement methods are used with minimal macro and port placement controls, then placement flexibility is maintained, but placement variability increases and quality of results decreases

Engineering Contradiction:
Improveplacement precisionVSAvoidplacement control complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The invention segments the placement control mechanism by introducing a placement director that divides the placement search space into manageable regions based on macro and port locations. This segmentation allows for localized control without requiring complex global constraints, thereby improving placement precision while managing complexity through spatial partitioning of the design area.

Inventive Principle:
Principle #1Segmentation

2Reliability

If placement search space is reduced using state group bounds, then placement variability is reduced and quality of results is improved, but placement flexibility is constrained

Engineering Contradiction:
Improveplacement consistencyVSAvoidplacement adaptability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The placement director dynamically adjusts the placement search space by deriving state group bounds from the current placement state and macro/port locations. This dynamic adaptation allows the system to maintain placement consistency through bounded search regions while preserving adaptability by adjusting bounds based on evolving placement requirements and design iterations.

Inventive Principle:
Principle #15Dynamics

3Manufacturing precision

If automatic state group bounds derivation is implemented, then placement control is refined and variance is reduced, but computational overhead increases

Engineering Contradiction:
Improveplacement control precisionVSAvoidplacement computation time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The invention performs preliminary action by pre-identifying macro and port locations and deriving state group bounds before the main placement optimization. This preliminary setup creates a structured framework that guides subsequent placement operations, reducing the computational burden during iterative optimization while maintaining precise placement control through pre-established bounds.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10114918B2Physical placement control for an integrated circuit based on state bounds file
Publication Date: 2018.10.30 ARM LTD
  • US10114918B2 patent drawing
  • US10114918B2 patent drawing
  • US10114918B2 patent drawing

AI summary

Various implementations described herein are directed to systems and methods for controlling physical placement of a circuit design. The systems and methods may extract state groups of the circuit design by deriving state groups from each logical hierarchy of the circuit design. At each level, available state points may be grouped by similarity and stored in a state groups collection alongside grouping terms. The systems and methods may generate a state bounds file that bounds locations of the state points in the circuit design. The state bounds file may be based on the extracted state groups and the grouping terms stored in the state groups collection. The systems and methods may control physical placement of the circuit design using the state bounds file.