IC Resource Placement Using Location-Based Timing Variation Data
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits, such as programmable logic devices, face performance variations due to process sensitivities and location-dependent timing differences, leading to deviations from ideal performance, which existing technologies fail to effectively compensate for.
Innovation Solution
A processor-based method that stores and compares performance-variation data between logically-equivalent resources, allowing for selective mapping, placement, and routing of design logic to compensate for these variations, using timing data correlated to physical locations to optimize resource utilization and simulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If transistor sizes are reduced to increase speed and density, then device speed and density are improved, but sensitivity to process variations increases
Solution Approach 1:
The patent measures and stores performance characteristics of programmable resources during manufacturing before the device is used by customers. This preliminary characterization captures process variations that occur during fabrication, and the stored data is later used to compensate for these variations during device operation, thereby maintaining reliability despite smaller transistor sizes.
Solution Approach 2:
The patent changes operational parameters of programmable resources based on their measured performance characteristics. By adjusting parameters such as timing, voltage, or other operational settings according to the stored performance data, the system compensates for process variations and maintains consistent device behavior across different manufacturing batches and process conditions.
2Speed
If device speeds are increased, then performance is improved, but susceptibility to timing variations increases
Solution Approach 1:
The patent performs preliminary timing measurements and stores timing characteristics for each programmable resource during manufacturing. These pre-captured timing data are then used to compensate for timing variations during device operation, allowing high-speed operation while maintaining timing precision through data-driven adjustments.
Solution Approach 2:
The patent implements a feedback mechanism where measured performance and timing data from actual device operation are stored and used to adjust and optimize device performance. This closed-loop approach allows the system to learn from actual timing behavior and make compensations that maintain precision even at high speeds.
3Manufacturing precision
If interconnect variations are reduced, then performance consistency is improved, but location and layout dependencies remain
Solution Approach 1:
The patent measures and stores performance characteristics for each specific programmable resource at its actual manufactured location during the manufacturing process. This preliminary characterization captures the specific interconnect variations and performance traits of each resource regardless of its location or layout, allowing the system to adapt to location-specific characteristics rather than requiring uniformity across all resources.
Data Source
AI summary
Various approaches are provided for generating an implementation of an electronic circuit design. In one embodiment, a processor-based method implements a design in an integrated circuit or IC (e.g., a programmable logic device. The method includes storing performance-variation data that represents location-based performance variations between logically-equivalent-programmable resources of the IC. The respective stored performance-variation data of at least two logically-equivalent-programmable resources of the IC are compared. The logic of the design is mapped, placed and routed on resources of the IC. The mapping, placing and routing includes, for an implementation of at least one subset of the logic of the design, selecting between the at least two logically-equivalent-programmable resources of the IC based on a result of the step of comparing respective stored performance-variation data of the at least two logically-equivalent-programmable resources. An implementation of the design is generated from the logic of the design placed and routed on the resources of the IC.