Integrated Circuit Polysilicon Perimeter Density Uniformity
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Solution Overview
Problem
As integrated circuit devices scale, variations in polysilicon perimeter density across a chip lead to performance parameter variations, such as threshold voltage differences, which current design verification tools fail to address effectively.
Innovation Solution
A method is developed to lay out integrated circuit designs with uniform polysilicon perimeter density by configuring and reconfiguring decoupling capacitor blocks to maintain desired decoupling capacitance, ensuring that local polysilicon perimeter densities are balanced across the chip, thereby minimizing performance parameter variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decoupling capacitor blocks are added to achieve desired decoupling capacitance, then power supply noise filtering is improved, but polysilicon perimeter density uniformity deteriorates
Solution Approach 1:
The patent applies local quality by configuring decoupling capacitor blocks with specific polysilicon perimeter densities that differ from other circuit blocks. Each decoupling capacitor block is locally optimized to compensate for polysilicon perimeter density variations in its surrounding region, thereby maintaining overall uniformity while providing the necessary decoupling capacitance for power supply noise filtering.
Solution Approach 2:
The patent changes the polysilicon perimeter density parameter of decoupling capacitor blocks to match target density values. By adjusting this parameter during layout configuration, the method achieves both the desired decoupling capacitance and uniform polysilicon perimeter density across the chip, resolving the contradiction between reliability and manufacturing precision.
2Productivity
If device scaling is continued to improve circuit functionality, then device density is improved, but performance parameter variations worsen
Solution Approach 1:
The patent controls the polysilicon perimeter density parameter during device scaling to maintain uniformity across the chip. By monitoring and adjusting this parameter, the method enables continued device scaling and increased device density while preventing performance parameter variations such as threshold voltage differences that would otherwise worsen with scaling.
3Manufacturing precision
If decoupling capacitor blocks are reconfigured to adjust polysilicon perimeter density, then polysilicon perimeter density uniformity is improved, but decoupling capacitance may deteriorate
Solution Approach 1:
The patent applies local quality by making targeted adjustments to decoupling capacitor block configurations only in regions where polysilicon perimeter density uniformity needs improvement. These localized reconfigurations are performed in a manner that maintains the overall decoupling capacitance, ensuring that power supply noise filtering performance is preserved while achieving the desired uniformity.
Data Source
AI summary
Disclosed are embodiments of forming an integrated circuit with a desired decoupling capacitance and with the uniform and targeted across-chip polysilicon perimeter density. The method includes laying out functional blocks to form the circuit according to the design and also laying out one or more decoupling capacitor blocks to achieve the desired decoupling capacitance. Then, local polysilicon perimeter densities of the blocks are determined and, as necessary, the decoupling capacitor blocks are reconfigured in order to adjust for differences in the local polysilicon perimeter densities. This reconfiguring is performed in a manner that essentially maintains the desired decoupling capacitance. Due to the across-chip polysilicon perimeter density uniformity, functional devices in different regions of the chip will exhibit limited performance parameter variations (e.g., limited threshold voltage variations). Also disclosed herein are embodiments of an integrated circuit structure formed according to the method embodiments and a design structure for the integrated circuit.