Per-cycle Power Analysis for IC Designs Using Logic Vector Propagation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current power analysis methods for integrated circuit designs, particularly cycle-based approaches, are computationally expensive and time-consuming, often requiring significant resources to estimate power consumption accurately on a per-cycle basis, which hinders efficient design evaluation and optimization.
Innovation Solution
A method that involves generating recorded logic vectors from timestamped value changes in a verification run, propagating these vectors through the integrated circuit design to infer logic values, and computing per-cycle power characteristics, utilizing parallel processing and caching to reduce computational overhead and enhance efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If cycle-based power analysis is performed accurately on a per-cycle basis, then power consumption estimation precision is improved, but computational resources and time consumption increase significantly
Solution Approach 1:
The patent segments the power analysis process into distinct phases: value change detection, logic vector generation, propagation through circuit cells, and power calculation. This segmentation allows each phase to be optimized independently and processed efficiently, reducing overall computational overhead while maintaining per-cycle precision
Solution Approach 2:
The patent performs preliminary actions by pre-computing logic vectors from value changes and propagating them through the circuit design before actual power calculation. This preliminary propagation establishes the logical state of each cell, enabling efficient power computation without redundant calculations during the actual measurement phase
2Measurement precision
If cycle-based power analysis is performed accurately on a per-cycle basis, then power consumption estimation precision is improved, but analysis time increases significantly
Solution Approach 1:
The patent maintains continuous useful action by processing logic vectors through the circuit design in a continuous flow without interruption. Value changes are continuously detected, logic vectors are continuously generated and propagated, and power characteristics are continuously calculated, eliminating idle time and redundant processing steps
Solution Approach 2:
By segmenting the analysis into discrete, manageable phases (value change detection, logic vector generation, propagation, power calculation), the patent enables parallel processing and optimization of each segment, significantly reducing total analysis time while maintaining per-cycle precision
3Measurement precision
If per-cycle power characteristics are computed, then power analysis accuracy is improved, but computational complexity increases
Solution Approach 1:
The patent extracts only the essential information needed for power calculation by focusing on value changes and their propagation through the circuit. Instead of analyzing all circuit parameters, it extracts and processes only the logic vectors and cell states that directly impact power consumption, simplifying the computational model
Solution Approach 2:
The patent changes the computational parameters from analyzing complete circuit states to tracking only value changes and logic vector propagations. This parameter transformation reduces the dimensionality of the problem while maintaining the accuracy needed for per-cycle power characteristic computation
Data Source
AI summary
A method includes: receiving value changes corresponding to timestamped logic value changes in recorded signals from a verification run of an integrated circuit (IC) design; generating recorded logic vectors from the value changes, each of the recorded logic vectors being associated with a corresponding signal identifier, each of the recorded logic vectors including a recorded logic values over a window of consecutive clock cycles computed from one or more value changes associated with the corresponding signal identifier and having timestamps within the window of consecutive clock cycles; determining, by a processor, inferred logic vectors including inferred logic values corresponding to signals output by cells of the IC design based on propagating the recorded logic values of the recorded logic vectors through the cells; and computing per-cycle power characteristics of the IC design based on the recorded logic vectors and the inferred logic vectors.