IC Power Calibration Circuit Without Separate ADC Blocks
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Solution Overview
Problem
Conventional integrated circuits (ICs) require separate large-size circuitries for power calibration and monitoring, leading to increased size and power consumption due to the inclusion of analog-to-digital converters (ADCs).
Innovation Solution
The IC incorporates a power calibration and monitoring system using a digital-to-analog converter (DAC), variable gain amplifier (VGA), comparator, and counter to generate and control differential feedback currents, allowing power calibration and monitoring with reduced component size and consumption by utilizing a single set of components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate circuitries for power calibration and monitoring are used, then power calibration and monitoring functions are achieved, but IC size increases
Solution Approach 1:
The patent combines power calibration and monitoring functions into a single integrated circuit block that shares common components including DAC, VGA, comparator, and counter. This merging eliminates the need for separate dedicated circuitries, thereby reducing overall IC area while maintaining both calibration and monitoring capabilities simultaneously
Solution Approach 2:
The integrated power calibration and monitoring system uses universal components that serve multiple purposes. The DAC generates feedback currents for both calibration and monitoring, the VGA amplifies signals for both functions, the comparator processes signals from both operations, and the counter provides digital output for both calibration status and power level monitoring
2Reliability
If separate circuitries for power calibration and monitoring are used, then power calibration and monitoring functions are achieved, but power consumption increases
Solution Approach 1:
The patent merges power calibration and monitoring circuitries into a single integrated system, eliminating redundant components and their associated power consumption. Shared components like the DAC, VGA, comparator, and counter are powered by the same supply network, reducing total energy usage compared to having separate independently powered circuitries
Solution Approach 2:
Universal components perform both calibration and monitoring functions, meaning their power consumption serves dual purposes. The DAC consumes power to generate feedback currents for calibration while the same currents are used for monitoring. The comparator processes signals for both functions, making its power consumption beneficial to both operations simultaneously
3Measurement precision
If ADCs are used for power calibration and monitoring, then accurate power measurement is achieved, but device complexity increases
Solution Approach 1:
Instead of using ADCs to convert analog power signals to digital form for measurement, the patent inverts the approach by using a DAC to generate analog feedback currents from digital codes, then using a comparator to convert the analog comparison result back to digital form. This inverted analog-digital conversion path achieves accurate power measurement while avoiding the complexity of ADC circuits
Solution Approach 2:
The patent substitutes the ADC (analog-to-digital converter) system with a different technical approach using DAC (digital-to-analog converter) and comparator. This substitution replaces the complex ADC conversion mechanism with a simpler digital control approach that uses analog feedback currents and voltage comparison to achieve the same measurement objective with reduced circuit complexity
Data Source
AI summary
An integrated circuit includes a functional circuit and a power calibration and monitoring system including a digital-to-analog converter (DAC), a variable gain amplifier (VGA), and a counter. The DAC generates a differential pair of feedback currents based on a digital count. The VGA generates a differential pair of amplified signals based on a magnitude difference between the differential pair of feedback currents and a differential pair of detection currents derived from a differential pair of node voltages associated with the functional circuit. The counter generates the digital count based on the differential pair of amplified signals. The differential pair of feedback currents is controlled such that the magnitude difference between the differential pair of detection currents and the differential pair of feedback currents is within a tolerance limit. A power associated with the functional circuit is calibrated and monitored based on the digital count.