Integrated Circuit Power Modeling via Clock Gating Signal Counting
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for estimating power consumption of integrated circuits at the system level are inaccurate and time-consuming, especially due to their reliance on developer experience and the complexity of modeling power states with multiple clock gating enable signals.
Innovation Solution
A method and apparatus that utilize clock gating enable signals to define power states and model power consumption, allowing for quick and accurate estimation of dynamic power consumption by determining the change rate of clock gating signals and extracting power states based on their number, thereby reducing modeling time and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional system level power consumption analysis is performed, then it can provide a general overview of power usage, but the accuracy deteriorates due to reliance on developer experience and comprehension
Solution Approach 1:
The patent replaces manual developer experience-based analysis with an automated computer-executed modeling system. The system automatically extracts clock gating enable signal information, determines modeling levels, and calculates power consumption without human intervention, thereby improving accuracy while reducing the complexity burden on developers.
Solution Approach 2:
The patent changes the parameter representation from complex sets of signal cases to a simplified counting approach. Instead of analyzing multiple individual signal states, the system uses the number of clock gating enable signals as a single representative parameter to define power states, which simplifies the modeling while maintaining accuracy.
2Productivity
If conventional system level power consumption analysis is performed, then it can be conducted at high level, but the modeling generation time extends
Solution Approach 1:
The patent performs preliminary extraction and processing of clock gating enable signal information during the design phase. By pre-processing the netlist to identify and count clock gating signals before final power consumption analysis, the system reduces the time required for subsequent modeling and generation operations.
Solution Approach 2:
The patent replaces manual, experience-based modeling processes with automated computer-executed algorithms that quickly extract, process, and model power consumption data. This automation dramatically reduces modeling generation time while maintaining system-level overview capabilities.
3Measurement precision
If power states are modeled using sets of clock gating enable signal cases, then detailed analysis is possible, but the device complexity and time consumption increase significantly
Solution Approach 1:
The patent merges multiple individual clock gating enable signal states into a single unified representation based on signal counting. Instead of treating each signal case separately, the system combines them into aggregated power states defined by the total number of enabled clock gating signals, which simplifies the model while preserving analytical detail.
Solution Approach 2:
The patent transforms the power state representation from a complex set of individual signal cases to a simplified parameter-based system. By using the count of clock gating enable signals as the defining parameter, the system reduces the dimensionality of the power state space while maintaining the ability to perform detailed power consumption analysis.
Data Source
AI summary
A method of modeling power consumption of an integrated circuit and an apparatus for supporting the same are provided. The method of modeling power consumption of an integrated circuit includes: grasping information about a clock gating enable signal of the integrated circuit; determining a modeling level using a change rate of the number of the clock enable signal; and extracting a power state according to the modeling level and the number of the clock gating enable signal and modeling power consumption in the power state. Thereby, because a power state can be defined with only the number of a clock gating enable signal, a dynamic power consumption amount can be quickly and accurately estimated.