Integrated Circuit Power Gating Retention Mode
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Solution Overview
Problem
Power gating in integrated circuits results in high energy costs during startup due to large power grid capacitance recharge and crowbar currents, as well as re-evaluation of logic values, which outweighs the energy savings from reduced leakage during idle periods.
Innovation Solution
The implementation of a retention mode using operational and retention mode transistors to maintain a low power voltage difference across combinatorial logic circuitry and a higher retention voltage difference across signal value storage circuitry, reducing crowbar currents and recharge energy, while allowing signal value retention and transitioning through a reset mode to minimize energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power gating is used to reduce leakage power during idle periods, then power consumption is reduced, but energy cost during power up increases due to large power grid capacitance recharge and crowbar currents
Solution Approach 1:
The power supply network is segmented into main power rails and virtual power rails. The virtual power rails are separated from the main power rails by retention mode transistors, allowing independent voltage control. This segmentation enables the circuit to reduce leakage power on virtual rails during idle periods while maintaining the ability to quickly restore full power without charging the entire power grid capacitance, thus resolving the contradiction between leakage reduction and power-up energy cost.
Solution Approach 2:
The patent changes the voltage parameter on virtual power rails during retention mode, maintaining a reduced voltage difference insufficient for full data processing but sufficient for signal retention. This parameter change allows the circuit to minimize leakage power while avoiding the need to recharge large capacitance from zero voltage, thereby reducing power-up energy costs.
2Loss of energy
If full power gating is used to minimize leakage, then leakage power is reduced, but crowbar currents and re-evaluation of logic values increase energy consumption during resumption
Solution Approach 1:
The retention mode transistors are preliminarily configured to maintain a small voltage difference across the combinatorial logic circuitry during retention mode. This preliminary action prevents the voltage from dropping to zero, thereby avoiding crowbar currents when power is restored and eliminating the need for logic value re-evaluation, while still achieving leakage power reduction during idle periods.
3Loss of energy
If power off mode is used for short idle periods, then leakage power is reduced, but energy cost on power up exceeds energy saved
Solution Approach 1:
The patent introduces a dynamic retention mode that adapts to short idle periods. The retention mode transistors dynamically maintain a reduced voltage state that prevents excessive leakage while avoiding the complete power-off state. This dynamic approach allows the circuit to quickly resume operation without the high power-up energy cost associated with full power gating, making it suitable for short idle periods where the energy saved would otherwise be less than the power-up cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the energy required to recharge the power grid and minimizes crowbar currents upon resuming operational mode, making the retention mode energy-efficient even for short idle periods, unlike power off mode which may incur higher energy costs upon resumption.
Implementation Method 1
said one or more first operational mode transistors and said one or more second operational mode transistors are in a low impedance state to provide an operating voltage difference sufficient to support data processing operations
Implementation Method 2
said one or more first operational mode transistors and said one or more second operational mode transistors are in a high impedance state
Implementation Method 3
said one or more first retention mode transistors and said one or more second retention mode transistors are in a low impedance state to provide a low power voltage difference insufficient to support data processing operations across said combinatorial logic circuitry and a retention voltage difference greater than said low power voltage difference and sufficient to support signal value retention
Data Source
AI summary
An integrated circuit includes a main power rail, a ground power rail as well as a virtual main power rail and a virtual ground power rail. Combinatorial logic circuitry is connected to draw its power from the virtual main power rail and the virtual ground power rail. Signal value storage circuitry is connected to draw its power from one of the main power rail and the ground power rail with the other power connection being to a virtual rail. The integrated circuit has an operational mode, a retention mode and a power off mode. In the retention mode, the voltage difference across the combinatorial logic circuitry is a low power voltage difference insufficient to support data processing operations whereas the voltage difference across the signal value storage circuitry is higher and is sufficient to support signal value retention within the signal value storage circuitry.