IC Power Grid Augmentation for Targeted IR-Drop Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Voltage drop issues in power grid networks of VLSI designs lead to timing constraints and cell failures due to peak current draws from standard cells on the same power rail, inefficient power grid routing, and clock tree structures, which existing power grid augmentation methods fail to adequately address.
Innovation Solution
A guided power grid augmentation method that determines minimum resistance paths, identifies target cells with significant voltage drop, and generates conductors within defined polygons to reduce IR-drop, thereby minimizing voltage drop and coupling capacitance, while maintaining efficient routing resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power grid augmentation is applied to all cells, then voltage drop is reduced, but device complexity and routing resources are consumed
Solution Approach 1:
The patent applies power grid augmentation selectively only to target cells that meet specific voltage drop criteria, rather than uniformly to all cells. This local quality approach ensures that augmentation resources are concentrated where most needed (cells with significant IR-drop), while avoiding unnecessary complexity in cells that already meet voltage requirements, thus resolving the contradiction between reliability improvement and device complexity reduction.
Solution Approach 2:
The patent segments the power grid augmentation process into distinct phases: voltage drop analysis, target cell identification based on criteria, polygon definition for target cells, and selective conductor generation. This segmentation allows the system to apply complexity only where necessary, reducing overall device complexity while maintaining reliability for critical cells.
2Reliability
If conductors are generated within polygons for all cells, then IR-drop is reduced, but routing resources decrease
Solution Approach 1:
The patent generates conductors within polygons only for identified target cells that meet voltage drop criteria, rather than for all cells. This local quality approach preserves routing resources in non-critical areas while concentrating conductor generation where it most effectively reduces IR-drop, thus resolving the contradiction between reliability improvement and productivity maintenance.
3Measurement precision
If minimum resistance paths are determined for all cells, then voltage drop analysis is comprehensive, but computation time increases
Solution Approach 1:
The patent performs preliminary voltage drop analysis using minimum resistance paths to identify target cells meeting specific criteria, then uses this pre-identified target set to guide subsequent conductor generation. This preliminary action approach maintains comprehensive analysis accuracy for critical cells while avoiding redundant computation for non-critical cells, thus resolving the contradiction between measurement precision and time loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The guided power grid augmentation effectively reduces IR-drop and coupling capacitance, ensuring cells meet timing constraints and improving overall IC design performance by targeting specific areas of high IR-drop, resulting in fewer power grid shapes and increased routing resources.
Implementation Method 1
determining a minimum resistance path for cells of an integrated circuit (IC) design to connect a cell to a respective IC tap
Implementation Method 2
determining a voltage drop value for each of the plurality of cells; identifying a plurality of target cells selected from the plurality of cells, wherein the voltage drop value of each of the plurality of target cells satisfy one or more voltage drop criteria
Data Source
AI summary
A method and system for guided power grid augmentation determines a minimum resistance path for cells within an integrated circuit (IC) design. The minimum resistance path traces a conducting wire connecting a pin of a cell to an IC tap within the IC design. A voltage drop value for each of the cells is determined so as to identify target cells having a voltage drop value that satisfies a voltage drop criteria. Polygons have defined size characteristics are defined around the minimum resistance paths of the target cells, and conductors, such as additional conductors, are generated within the defined polygons.