Integrated Circuit Power Grid Segmentation for Leakage Reduction
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Solution Overview
Problem
Integrated circuits consume power unnecessarily due to transistors receiving operating power even when not actively processing signals, limiting battery life in portable devices.
Innovation Solution
Implementing a power management system with two power grids, where one grid is powered down in idle mode to reduce leakage current, while the other remains active, specifically targeting combinatorial logic circuitry for power savings without complex routing schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power is supplied to all transistors in the integrated circuit, then all functional blocks can operate actively, but power consumption increases due to leakage current in idle transistors
Solution Approach 1:
The power supply network is segmented into multiple independent power grids (first power grid and second power grid) that can be independently controlled. Sequential logic circuitry is connected to the first power grid while combinatorial logic circuitry is connected to the second power grid, allowing selective powering of different circuit segments based on operational requirements.
Solution Approach 2:
The patent implements dynamic power management by enabling the integrated circuit to switch between different operating states: a first operating state where both power grids are active for full functionality, and a second operating state where only the first power grid remains active to reduce power consumption during idle periods for combinatorial logic operations.
2Use of energy by moving object
If power is removed from combinatorial logic circuitry to reduce power consumption, then leakage current decreases, but the circuit cannot process signals when needed
Solution Approach 1:
The patent implements periodic switching between operating states based on signal processing requirements. The power management system transitions between the first operating state (both power grids active) and the second operating state (only first power grid active) according to the need for combinatorial logic operations, enabling power savings during idle periods while maintaining readiness when signals need processing.
Solution Approach 2:
The patent introduces a power management system as an intermediary layer between the power sources and the logic circuitry. This intermediary controls the distribution of power to different circuit blocks, enabling selective activation of combinatorial logic circuitry through the second power grid only when needed, while maintaining sequential logic circuitry readiness through the first power grid.
3Device complexity
If a unified power supply is used for all logic circuitry, then the power distribution is simple, but power savings cannot be achieved for specific idle circuit blocks
Solution Approach 1:
The unified power supply is segmented into at least two separate power grids: a first power grid connected to sequential logic circuitry and a second power grid connected to combinatorial logic circuitry. This segmentation allows independent control of power distribution to different logic blocks, enabling the second power grid to be deactivated when combinatorial logic is not needed, thereby reducing overall power consumption while maintaining a relatively simple overall structure.
4Speed
If transistors remain powered during idle mode, then they can immediately process signals, but leakage current causes continuous power consumption
Solution Approach 1:
The patent implements dynamic power state transitions for different circuit blocks based on operational mode. In idle mode, the second power grid is deactivated to stop leakage current in combinatorial logic transistors. When signal processing is needed, the system transitions to the first operating state, reactivating the second power grid and enabling immediate signal processing capability without maintaining continuous power consumption during idle periods.
Data Source
AI summary
A method for reducing power consumption in an integrated circuit and an integrated circuit having a power reduction feature. The integrated circuit has at least two functional circuit blocks and two upper supply rails. A first upper supply rail is coupled to the first functional circuit block and a second upper supply rail is coupled to the second functional circuit block. A lower supply rail is coupled to the first and second functional circuit blocks. In an active mode of operation, a first source of operating potential is electrically coupled to the first upper supply rail and a second source of operating potential is electrically coupled to the second upper supply rail. In an idle mode of operation, the first upper supply rail remains electrically coupled to the first source of operating potential and the second source of operating potential is electrically decoupled from the second functional circuit block.