Programmable Integrated Circuit Power Loss Emulation
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Solution Overview
Problem
Programmable integrated circuits lack the capability to accurately emulate power loss events, which are critical for simulating the behavior of application-specific integrated circuits (ASICs), leading to inconsistencies in testing and debugging, as they cannot replicate the random state changes that occur in ASICs with multiple power domains during power cycling.
Innovation Solution
A programmable integrated circuit is equipped with an encoder-decoder pair and a pseudo-random number generator to alter data content during power loss events, effectively corrupting or randomizing the state of non-resettable circuits, thereby mimicking the behavior of ASICs and detecting hardware-level defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a programmable integrated circuit is used for hardware emulation, then the time to market and cost are reduced compared to ASIC, but the ability to accurately emulate power loss events is lost
Solution Approach 1:
The patent creates a copy of the ASIC design on a programmable integrated circuit (FPGA) that includes power domain structures and non-resettable circuits mimicking the target ASIC architecture. This copy enables hardware emulation with realistic power loss behavior while maintaining the speed and cost advantages of FPGA-based prototyping.
Solution Approach 2:
The patent changes the operational parameters of the programmable circuit by introducing configurable power domain structures, controllable power loss injection mechanisms, and state preservation logic that alters how the circuit responds to power events, enabling accurate power loss emulation without sacrificing FPGA performance benefits.
2Reliability
If power loss events are emulated on a programmable integrated circuit, then ASIC behavior accuracy is improved, but the device complexity increases
Solution Approach 1:
The patent segments the emulated circuit into distinct power domains, each with its own power control logic and state management. This segmentation allows independent control of power loss events in different circuit regions while maintaining overall system manageability and reducing the complexity burden through modular organization.
Solution Approach 2:
The patent introduces intermediary control logic and wrapper circuits that mediate between the programmable circuit resources and the emulated ASIC behavior. These intermediaries handle the complexity of power loss simulation, state preservation, and random state generation, shielding the core emulation logic from excessive complexity while achieving accurate ASIC behavior replication.
3Difficulty of detecting and measuring
If random state changes are implemented during power loss events, then detection of hardware defects is improved, but the ease of operation decreases
Solution Approach 1:
The patent implements dynamic state management where non-resettable circuits maintain their state across power loss events, and random state changes are injected only when appropriate (during actual power domain isolation). This dynamic approach enables realistic defect detection while maintaining operational simplicity through automated state tracking and controlled randomness injection.
Solution Approach 2:
The patent performs preliminary configuration of power domain structures, non-resettable circuit states, and power loss event parameters before emulation begins. This preliminary setup automates the complexity of random state generation and defect detection scenarios, reducing operational burden during actual testing while maintaining high defect detection capability.
Data Source
AI summary
Programmable integrated circuits may be used to perform hardware emulation of an application-specific integrated circuit (ASIC) design. The ASIC design may be loaded onto the programmable integrated circuit as a circuit under test (CUT). During hardware emulation operations, an emulation host may be used to coordinate testing of the CUT on the programmable device. To help emulate a power gating event for the ASIC design, the programmable device may be provided with an encoder at the input of the CUT, a decoder at the output of the CUT, and a pseudorandom number generator (PRNG) that outputs a value for adjusting the encoder and decoder. The value output from the PRNG stays fixed when there is no power loss, but will change to a new value during a power gating event. Operated in this way, the data read out from the CUT after the power gating event is effectively corrupted.