Integrated Circuit Standard Cell Power Rail Routing
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Solution Overview
Problem
As semiconductor technology advances and transistor sizes shrink, the physical layout of standard cells becomes increasingly complex, leading to issues with metal layer connectivity, which can require additional interconnect levels, increasing manufacturing costs and cycle time.
Innovation Solution
The method involves deploying an active area in a standard cell with overlapping gate electrodes and metallic line structures, routing a power rail orthogonal to the metallic lines, and using connection plugs to electrically connect nodes, thereby avoiding the need for additional metal layers and simplifying the design within a pre-defined area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor sizes are shrunk to advance semiconductor technology, then device integration density is improved, but physical layout complexity increases leading to metal layer connectivity issues
Solution Approach 1:
The patent introduces a vertical dimension by stacking multiple standard cells in the third dimension (Z-axis) to form a 3D integrated circuit structure. This allows metal layers to connect between stacked cells via vertical vias, reducing the need for additional horizontal metal interconnect layers and simplifying the overall metal layer connectivity while maintaining high device integration density.
2Reliability
If additional metal layers are added to resolve connectivity issues, then electrical connectivity is improved, but manufacturing cost and cycle time increase
Solution Approach 1:
Instead of adding more horizontal metal layers to resolve connectivity issues, the patent utilizes the vertical dimension by stacking standard cells and providing direct vertical electrical connections between them. This approach maintains reliable electrical connectivity while avoiding the increased manufacturing complexity and cost associated with additional metal interconnect layers.
3Productivity
If standard cells are designed with pre-defined area constraints, then design efficiency is improved, but routing flexibility is reduced
Solution Approach 1:
The patent enables dynamic routing flexibility within pre-defined standard cell area constraints by allowing metal lines to extend beyond the immediate cell boundaries in controlled regions and by providing multiple vertical via paths for inter-cell connections. This maintains design efficiency through standardized cell structures while preserving routing adaptability for various design configurations.
Data Source
AI summary
An integrated circuit includes a first standard cell over a substrate, a power rail, and a first connection plug. The first standard cell includes an active area, at least one gate electrode overlapping the active area of the first standard cell, and at least one metallic line structure overlapping the active area of the first standard cell. The at least one metallic line structure is substantially parallel to the gate electrode. The power rail is substantially orthogonal to the at least one metallic line structure of the first standard cell. The power rail overlaps the at least one metallic line structure of the first standard cell, and the power rail has a flat edge extending through the first standard cell. The first connection plug is at a region where the power rail overlaps the at least one metallic line structure of the first standard cell.