IC Power Shutoff Emulation via Domain Segmentation
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Solution Overview
Problem
Conventional hardware-based emulation systems for integrated circuits (ICs) fail to effectively verify power shutoff behavior and related power management functions in low-power designs, as these systems typically apply power optimization techniques during the physical implementation phase, altering the design intent and disrupting the RTL to GDSII implementation flow, thus lacking comprehensive power management verification capabilities.
Innovation Solution
A method and apparatus for modeling power management in ICs, including specifying a power architecture with multiple power domains, determining an emulation module with hardware elements for simulating power levels, power shutoff, cell isolation, and state retention, and using instrumentation logic to capture and verify power management characteristics, enabling improved verification of power shutoff behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional hardware-based emulation systems are used, then emulation speed is fast, but power shutoff behavior verification capability is insufficient
Solution Approach 1:
The system segments the IC design into multiple power domains, each independently controllable for power shutoff verification. The emulation system is divided into domain description modules that separately define and verify power management behavior in each domain, enabling comprehensive verification without sacrificing emulation speed.
Solution Approach 2:
An intermediate power domain description is introduced as a formal specification layer between the RTL design and the emulation system. This intermediate representation enables the emulation system to verify power shutoff behavior by providing explicit power domain definitions and transition rules without requiring modification of the core emulation architecture.
2Loss of energy
If power optimization techniques are applied during physical implementation phase, then power management is improved, but design intent is altered and RTL to GDSII flow is disrupted
Solution Approach 1:
Power domain descriptions and verification rules are prepared in advance during the design phase, before physical implementation. This preliminary specification of power management behavior ensures that design intent is preserved and verified early, preventing disruptions to the RTL to GDSII flow while still enabling effective power optimization.
Solution Approach 2:
The system implements feedback verification where the emulation system checks power management behavior against the specified power domain descriptions. This feedback mechanism ensures that power optimization techniques maintain consistency with design intent by automatically verifying that implemented power management matches the original specifications.
3Device complexity
If conventional emulation systems are used, then verification process is simple, but power management verification capabilities are lacking
Solution Approach 1:
The emulation system is enhanced with universal power domain description modules that can verify power management behavior across different IC designs and power architectures. These modules provide multi-functional verification capabilities for various power management scenarios (power shutoff, retention, isolation) without requiring separate verification systems for each case.
Data Source
AI summary
A method for modeling power management in an integrated circuit (IC) includes: specifying a circuit design and a power architecture for the IC, the power architecture including a plurality of power domains for specifying power levels in different portions of the IC; determining an emulation module for the IC by including one or more hardware elements for modeling the power architecture in the emulation module; and using the emulation module to simulate changing power levels in one or more power domains of the IC including a power shutoff in at least one power domain.