IC Power Supply Control via Segmented Header Transistors
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Solution Overview
Problem
Existing techniques for switching on power supply to virtual power rails in integrated circuits result in excessive in-rush currents, leading to erroneous operation and potential damage, due to the need for safe margins that increase latency.
Innovation Solution
The implementation of a controller circuitry that divides transistors into sets, switching them from a high impedance to a low impedance state in a predetermined sequence based on sensed voltage, allowing for reduced margin and higher in-rush currents while minimizing latency, using Schmitt trigger circuits for voltage sensing and programmable trigger values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If header and/or footer transistors are switched on to connect logic circuitry to power supply, then power supply is restored to active state, but excessive in-rush current flows charging the capacitance of logic circuitry and virtual power rails
Solution Approach 1:
The transistors are divided into multiple sets that are switched on in a predetermined sequence. This segmentation allows the total transistor count to be increased without proportionally increasing in-rush current, as transistors are activated gradually rather than simultaneously.
Solution Approach 2:
Controller circuitry switches on transistors in advance in a controlled sequence before full power supply activation is needed. This preliminary action allows capacitance to charge gradually through controlled current paths, preventing excessive in-rush current while ensuring power is ready when needed.
2Object-generated harmful factors
If safe margin is applied to control switching on of header and/or footer transistors to prevent excessive in-rush current, then in-rush current is kept within acceptable levels, but latency increases due to slower switching on
Solution Approach 1:
By segmenting transistors into sets activated in sequence, the system can use more transistors overall while controlling in-rush current through gradual activation. This reduces the need for excessive safe margins on individual transistor switching timing.
Solution Approach 2:
Controller circuitry monitors the state of transistors and adjusts switching timing based on actual conditions rather than relying on conservative fixed margins. This feedback mechanism allows optimization of switching timing to minimize latency while preventing excessive in-rush current.
3Loss of time
If more header and/or footer transistors are switched on to reduce latency, then switching speed increases, but in-rush current exceeds acceptable levels
Solution Approach 1:
Transistors are organized into multiple sets that can be activated in parallel within each time slot of the sequence. This allows maximum utilization of transistor capacity at each stage without overwhelming the power supply, reducing overall latency while controlling in-rush current.
Solution Approach 2:
Transistors are switched on in periodic time slots rather than all at once. This periodic activation distributes the in-rush current over time, allowing more transistors to be used overall while maintaining safe current levels at any given moment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces latency by allowing higher in-rush currents within safe limits, accommodating process, voltage, and temperature variations, and ensuring efficient power switching between sleep and operational states.
Implementation Method 1
controller circuitry senses a voltage of said second power supply conductor and controls switching of said sets from said high impedance state to said low impedance state following said predetermined sequence in dependence upon said voltage
Implementation Method 2
a plurality of transistors configured to provide a current path from said first power supply conductor to said second power supply conductor
Implementation Method 3
controller circuitry coupled to said plurality of transistors and configured to control said plurality of transistors to switch from a high impedance state to a low impedance state of varying degree
Implementation Method 4
logic circuitry coupled to said second power supply conductor and configured to draw electrical power from said second power supply conductor
Data Source
AI summary
An integrated circuit 2 is provided with a first power supply conductor 8 coupled via header transistors 14 to 26 to a second power supply conductor 10. Logic circuitry 4, 6 draws its power supply from the second power supply conductor. When switching from a sleep mode to an operating mode the header transistors 14 to 26 are divided into a plurality of sets of transistors which are switched on in a predetermined sequence using controller circuitry 28. The controller circuitry 28 senses the voltage of the second power supply conductor 10 to determine when each set of header transistors should be switched on. In this way, the in-rush current within the integrated circuit 2 associated with the switch from the sleep state to the operating state can be held within a predetermined range of a target in-rush current.