Integrated Circuit Process Corner Mask Segmentation
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in efficiently creating layouts for semiconductor chips that balance performance and power consumption, as automated design tools often fail to meet requirements for performance, power, signal integrity, and process yield, leading to the need for manual customization of cells and process corners.
Innovation Solution
The use of a process corner mask that defines different sets of parameters for distinct functional blocks within an integrated circuit, allowing for the integration of high-performance and low-power transistors on the same die, with a single mask indicating areas for each process corner, enabling dynamic power management by selecting appropriate power-performance states based on operational conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-performance process corner is selected for the entire die, then performance is improved, but power consumption increases due to appreciable leakage current
Solution Approach 1:
The die is divided into multiple process corners, with each functional block assigned to a specific process corner. This segmentation allows different regions of the die to have different transistor characteristics, enabling high-performance blocks to use high-performance process corners while low-power blocks use low-power process corners, thus resolving the contradiction between performance and power consumption at the system level
Solution Approach 2:
Different process corners are applied to different functional blocks based on their specific requirements. Critical performance blocks receive high-performance process corners, while non-critical blocks receive low-power process corners. This local optimization ensures that power consumption is reduced in areas where high performance is not essential, while maintaining high performance where needed
2Use of energy by moving object
If a low-power process corner is selected for the entire die, then power consumption is reduced, but performance decreases due to reduced leakage current
Solution Approach 1:
The die is segmented into multiple process corners, allowing low-power process corners to be applied to non-critical functional blocks where performance requirements are minimal. This segmentation ensures that power consumption is reduced in appropriate areas without sacrificing overall system performance, as critical blocks can still utilize high-performance process corners
Solution Approach 2:
Low-power process corners are selectively applied to functional blocks where performance requirements are less stringent. This local application of low-power characteristics reduces overall power consumption while maintaining high performance in critical blocks that require high-performance process corners, thus resolving the contradiction between power reduction and performance maintenance
3Productivity
If automated synthesis tools are used, then design cycle is shortened, but performance and power requirements are not met
Solution Approach 1:
The design process is segmented into automated synthesis for initial layout generation and manual customization for critical functional blocks. This segmentation allows the majority of the design to be completed automatically, maintaining short design cycles, while critical blocks receive manual optimization to meet stringent performance and power requirements
Solution Approach 2:
Automated synthesis tools are used to generate initial layouts and configurations, providing a starting point that satisfies basic requirements. This preliminary automated action establishes the foundation of the design quickly, after which manual customization can be applied to critical blocks to fine-tune performance and power characteristics, thus maintaining efficiency while meeting requirements
Data Source
AI summary
A system and method for creating layout for semiconductor chips are described. In various implementations, an integrated circuit includes at least a first functional block and a second functional block. The first functional block includes circuitry that has a first set of parameters of a first process corner. The second functional block includes circuitry that has a second set of parameters of a second process corner different from the first set of parameters of the first process corner. For a same set of operating conditions, the second functional block has device characteristics different from device characteristics of the first functional block based on the first process corner and the second process corner being different from one another. The integrated circuit is fabricated with a process corner mask that indicates which areas of the die use the first process corner and which areas use the second process corner.