IC Process Characterization via Segmented Test Structures
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Solution Overview
Problem
Integrated circuit (IC) manufacturing processes face challenges in characterizing the effects of sub-nominal device features on test chips, which can cause random defectivity issues and reduce the coverage of the manufacturing process characterization.
Innovation Solution
A system that receives a layout with varied test structures, fabricates wafers using different process settings, and generates a process model based on the effects of design variables and process settings on performance characteristics, such as yield and pass/fail rates, to predict performance for untested design variable values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If test devices with sub-nominal device features are included in the test chip, then the coverage of IC manufacturing process characterization is improved, but random defectivity issues occur due to features breaking off during manufacturing
Solution Approach 1:
The test chip is divided into multiple separate test devices, each containing sub-nominal device features. By segmenting the test structures into isolated units rather than having them distributed across the entire chip, the patent prevents defect propagation while maintaining comprehensive process coverage. Each segmented test device can be independently characterized without risking defects on other parts of the chip.
2Reliability
If test devices with sub-nominal device features are excluded from the test chip, then defectivity issues are reduced, but the coverage of IC manufacturing process characterization is reduced
Solution Approach 1:
The patent performs preliminary characterization of sub-nominal device features by fabricating dedicated test devices specifically designed to test these features before they are used in production circuits. This preliminary action allows the manufacturing process to be fully characterized for sub-nominal features without risking defectivity in the actual product circuits, as the test structures are isolated and can be excluded from production use.
3Adaptability or versatility
If a comprehensive test layout including various design variables is used, then the process characterization coverage is improved, but the complexity of the test chip increases
Solution Approach 1:
The complex test layout is segmented into multiple independent test devices, each focusing on specific design variables or feature sets. This segmentation reduces the complexity any single test structure must handle while maintaining comprehensive overall coverage. Each test device can be optimized for specific characterization goals without requiring the entire chip to accommodate all variations.
Data Source
AI summary
A system that characterizes an integrated circuit manufacturing process is presented. During operation, the system receives a layout which includes a plurality of test structures for semiconductor devices, wherein each test structure varies one or more design variables. The system then fabricates a plurality of wafers based on the layout, wherein each wafer in the plurality of wafers is fabricated using one of a plurality of process settings. Next, the system obtains performance characteristics for the plurality of test structures on the plurality of wafers. The system then generates a process model that is based on at least the effect that values for the one or more design variables and the plurality of process settings have on the performance characteristics of the plurality of test structures.