Integrated Circuit Propagation Time Error Detection
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Solution Overview
Problem
Integrated circuits face challenges in identifying propagation time errors, particularly at higher clock frequencies, which can lead to malfunctions, and existing methods are complex and costly due to the need for multiple input pins and complex programming.
Innovation Solution
The method involves using a multiplicity of scan cells connected as shift registers in a scan chain shift mode, with dedicated clock domains and a multiplexer to generate clock signals from a functional clock input, allowing for propagation time error identification with reduced control complexity and cost by reusing the PLL and simplifying the clock tree creation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple input pins and complex programming are used to identify propagation time errors, then testing accuracy is improved, but device complexity and cost increase
Solution Approach 1:
The patent makes the functional clock input and existing scan chain infrastructure serve dual purposes: normal functional operation and propagation time error testing. By reusing the functional clock input for test clock signals and the existing scan chain for both functional testing and propagation time measurement, the invention eliminates the need for dedicated test pins and complex test programming, thereby reducing device complexity while maintaining testing accuracy
Solution Approach 2:
The patent enables the integrated circuit's own functional clock input and scan chain to serve the testing function without requiring external dedicated test equipment or additional control infrastructure. The circuit uses its own operational resources to perform self-testing for propagation time errors, eliminating the need for external complex testing apparatus
2Measurement precision
If dedicated test infrastructure is used for propagation time error identification, then measurement precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent makes the functional clock input and existing scan chain infrastructure serve dual purposes: normal functional operation and propagation time error testing. By reusing the functional clock input for test clock signals and the existing scan chain for both functional testing and propagation time measurement, the invention eliminates the need for dedicated test pins and complex test programming, thereby reducing device complexity while maintaining testing accuracy
Solution Approach 2:
The patent enables the integrated circuit's own functional clock input and scan chain to serve the testing function without requiring external dedicated test equipment or additional control infrastructure. The circuit uses its own operational resources to perform self-testing for propagation time errors, eliminating the need for external complex testing apparatus
3Measurement precision
If complex clock tree creation is used for testing, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent makes the functional clock input and existing scan chain infrastructure serve dual purposes: normal functional operation and propagation time error testing. By reusing the functional clock input for test clock signals and the existing scan chain for both functional testing and propagation time measurement, the invention eliminates the need for dedicated test pins and complex test programming, thereby reducing device complexity while maintaining testing accuracy
Data Source
AI summary
An integrated circuit is disclosed. In one embodiment, for each clock domain there is at least one clock driver which is situated in the integrated circuit and which drives circuits situated in the clock domain. Each clock driver in the clock domain contains a clock input and an enable input, and its output outputs the clock received at the clock input if an enable signal is applied to the enable input. The clock driver receives a clock derived from the signal at the functional clock input, and the enable signal is connected in line with the values stored in the signal sequence registers if there is a signal change at the scan clock input when the scan chain shift mode has been switched off.