Integrated Circuit Radiation Immunity via Positive Substrate Bias
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Solution Overview
Problem
Conventional methods to address single event upsets (SEUs) in integrated circuits, caused by radiation, are ineffective as they increase the SEU rate due to the repelling of minority carriers by highly doped buried layers, leading to data corruption and performance issues.
Innovation Solution
An integrated circuit design featuring an n-type wafer with a p-type epitaxial layer and an n-well, where the n-type wafer is positively biased to attract excess minority carriers, forming reverse-biased p-n junctions to dissipate excess charge, thereby reducing the impact of SEUs without increasing die size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a highly doped buried P+ layer is used to sink minority carriers, then the recombination rate is improved, but the SEU rate increases due to repelling of minority carriers
Solution Approach 1:
The patent inverts the conventional approach by using a lightly doped or intrinsic buried layer instead of a highly doped P+ layer, and by applying positive bias to the n-type substrate to attract minority carriers, thereby resolving the contradiction between recombination rate and SEU rate
Solution Approach 2:
The patent changes the doping concentration parameter of the buried layer from highly doped to lightly doped or intrinsic, and changes the electrical bias parameter of the substrate from neutral to positive, thereby simultaneously improving recombination rate and reducing SEU rate
2Reliability
If conventional techniques are used to detect and correct data errors, then data corruption is addressed, but the entire memory must be reloaded which reduces productivity
Solution Approach 1:
The patent implements preliminary action by pre-configuring the memory cell structure with reverse-biased p-n junctions and positive substrate bias that automatically sink minority carriers before they can cause data corruption, preventing errors before they occur rather than detecting and correcting them after the fact
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces the SEU rate by effectively attracting and dissipating minority carriers, improving radiation immunity and preventing data corruption without occupying additional area, outperforming conventional CMOS technology and silicon-on-insulator memory cell arrangements.
Implementation Method 1
the n-type wafer is positively biased to attract excess minority carriers in the p-type epitaxial layer
Implementation Method 2
forming reverse-biased p-n junctions to dissipate excess charge
Data Source
AI summary
An integrated circuit device having improved radiation immunity is described. The integrated circuit device comprises an n-type wafer having a first surface and a second surface; a p-type epitaxial layer formed on the first surface of the n-type wafer, the p-type epitaxial wafer having first elements storing charge; and an n-well formed in the p-type epitaxial layer, the n-well having second elements storing charge; wherein the n-type wafer is positively biased to attract excess minority carriers in the p-type epitaxial layer. A method of improving radiation immunity in an integrated circuit is also described.