Integrated Circuit Security via Random Clock Period Variation
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Solution Overview
Problem
Integrated circuits are vulnerable to side channel attacks, which exploit statistical analysis of emissions like power noise and timing information to gain access to secret keys, posing a security threat.
Innovation Solution
Implementing a secure domain with a clock signal that varies randomly over cycles, using a delay-line based oscillator with selectively incorporated delay elements and a pseudorandom bit sequence generator to de-correlate side-channel traces, thereby making statistical analysis difficult.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy cycles are inserted into critical logic to protect against side channel attacks, then security against side channel attacks is improved, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the clock period variable rather than fixed. The protection clock portion dynamically adjusts the clock period to vary randomly over at least some cycles of operation, creating a non-periodic clock signal that disrupts the temporal correlations exploited by side channel attacks while avoiding the continuous power overhead of dummy cycles
Solution Approach 2:
The patent changes the parameter of clock period from a constant value to a variable value that fluctuates randomly. By modifying the clock period parameter dynamically, the system disrupts the statistical patterns in power consumption and electromagnetic emissions that side channel attacks rely on, achieving security without the energy cost of executing unnecessary dummy operations
2Reliability
If dummy cycles are executed to randomize execution time, then protection against timing attacks is improved, but circuit power consumption increases
Solution Approach 1:
The patent makes the clock signal dynamic by varying its period randomly, which naturally randomizes the execution time of operations in the secure domain. This dynamic timing variation provides protection against timing attacks without requiring the insertion of dummy cycles, thereby avoiding the associated power consumption increase
3Reliability
If a switched capacitance supply is used to reduce power signature, then power analysis resistance is improved, but device complexity increases
Solution Approach 1:
The patent uses a dynamic clock period approach that inherently masks power consumption patterns. By varying the clock period randomly, the power consumption profile becomes non-stationary and difficult to analyze statistically, providing power analysis resistance through timing variation rather than through complex power management circuits like switched capacitance supplies
4Measurement precision
If statistical analysis of side channel traces is performed, then key extraction capability is improved, but trace alignment difficulty increases when clock period varies randomly
Solution Approach 1:
The patent applies dynamics by varying the clock period randomly, which de-synchronizes the temporal alignment between different power traces. This dynamic timing variation makes it extremely difficult for attackers to align traces for statistical analysis, as the random clock variations introduce unpredictable time shifts that prevent consistent correlation across multiple traces
Solution Approach 2:
The patent converts the harmful effect of variable timing into a beneficial security feature. The random clock period variations, which would normally be considered a source of timing jitter and potential harm to performance, are instead exploited to create unalignable power traces that resist statistical analysis, turning a potential weakness into a security strength
Data Source
AI summary
An integrated circuit has multiple clock domains. At least one of the clock domains is a secure domain including a protection clock portion. The protection clock portion is arranged to produce a clock signal having a clock period which varies randomly over at least some cycles of operation. The clock signal is arranged to clock one or more components in the secure domain.