Integrated Circuit Rear-Face Attack Detection via Resistance Monitoring
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Solution Overview
Problem
Integrated circuits are vulnerable to attacks from the rear face, where hackers etch cavities and create electrical contacts to analyze or modify the circuit, posing a risk to confidentiality and operational integrity.
Innovation Solution
Incorporating detection circuits with bias contacts and transistors that monitor electrical resistance between specific points on the circuit, generating an alert signal when abnormal resistance is detected, indicating a potential attack, allowing for countermeasures such as shutting down the circuit or destroying sensitive information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the integrated circuit is left without additional protection structures, then the manufacturing process remains simple and production cost is low, but the circuit becomes vulnerable to rear-face attacks where hackers can etch cavities and create unauthorized electrical contacts
Solution Approach 1:
The protection system is segmented into multiple independent detection circuits, each monitoring a specific conductive track. Each detection circuit includes its own detection transistor and resistance measurement capability, allowing distributed security monitoring without requiring a centralized complex protection structure.
Solution Approach 2:
The detection circuits are integrated within the existing circuit architecture by nesting detection transistors in series with the conductive tracks. The detection structures are embedded within the same semiconductor substrate, utilizing the existing layer structure and doping regions to minimize additional complexity.
2Reliability
If detection circuits are added to monitor each conductive track, then the security against unauthorized access is improved, but the manufacturing complexity and production cost increase
Solution Approach 1:
The detection transistors and associated structures are formed during the standard CMOS fabrication process before final circuit assembly. The P-type detection transistors are created using preliminary ion implantation and thermal diffusion steps that prepare the semiconductor substrate for subsequent circuit formation, ensuring detection capability is built-in from the start.
Solution Approach 2:
The invention utilizes changes in electrical resistance as the primary detection mechanism. When a hacker creates an unauthorized contact, it alters the resistance characteristics of the monitored conductive track. The detection circuits measure these resistance changes to identify attacks, leveraging fundamental electrical property changes rather than requiring complex mechanical or optical detection systems.
3Productivity
If the circuit operates continuously without interruption, then productivity and operational efficiency are maintained, but the circuit remains exposed to attacks during operation
Solution Approach 1:
The detection circuits operate continuously alongside the main circuit functions, providing uninterrupted security monitoring. The resistance measurement capability is always active, allowing immediate detection of unauthorized contacts regardless of the circuit's operational state, thus maintaining both productivity and security simultaneously.
Solution Approach 2:
The detection circuits provide continuous feedback about the integrity of conductive tracks. When resistance changes indicate an unauthorized contact, the system generates an alert signal that can trigger countermeasures. This feedback mechanism allows the circuit to maintain operational awareness and respond to threats in real-time without requiring interruption of normal functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively detects and prevents unauthorized access by identifying and responding to attempts to create cavities on the rear face of the integrated circuit, ensuring the security and integrity of the circuit's operation.
Implementation Method 1
Each detection circuit (60) comprises a detection transistor (52) connected in series with the strip (7) between two bias contacts (11, 13) and adapted to measure an electrical resistance between the two bias contacts (11, 13)
Data Source
Figure 1A
Figure 1B~1C
Figure 2A~2B
AI summary
The invention relates to an integrated circuit comprising a plurality of first semiconductor bands (7) of a first type of conductivity and second semiconductor bands (9) of a second type of conductivity arranged alternately and contiguously on a region (5) of the second type of conductivity, comprising for each of the first bands: a plurality of bias contacts (11); for each bias contact, a switch (52) adapted to apply a potential (GND) on the bias contact; two detection contacts (56, 58) disposed at the ends of said first band; and a detection circuit (60) whose activation causes the opening of the switches and the comparison to a threshold of the resistance between the detection contacts.