Automated IC Redesign with Relaxed Spacing Rules
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Solution Overview
Problem
The challenge lies in efficiently updating existing integrated circuit (IC) designs to take advantage of manufacturing improvements, such as EUV processing, without uniformly reducing all design aspects, due to constraints in other technologies like insulator quality and feature alignment, making it time-consuming and costly to revise IC designs.
Innovation Solution
The method automatically converts original IC designs to reduced designs with smaller spacings between elements, using a single lithographic mask for via placement, and evaluates movement flexibility in wiring levels to uniformly reduce feature sizes in flexible regions, replacing single vias with multiple vias or via bars, and adjusting conductive line ends and widths, while maintaining functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If manufacturing improvements such as EUV processing are implemented, then IC features can be made smaller and spacing rules can be relaxed, but the time and cost required to revise existing IC designs increases significantly
Solution Approach 1:
The system automatically changes design parameters (spacing rules, feature sizes) to match new manufacturing capabilities. It takes the original IC design and applies relaxed spacing rules and reduced minimum spacing values to generate a redesigned layout that utilizes the improved EUV manufacturing precision without manual intervention.
Solution Approach 2:
The system creates a copy of the original IC design and automatically modifies it to take advantage of new manufacturing capabilities. Rather than manually redrawing the entire design, it copies the original layout and systematically adjusts spacing and feature dimensions according to the new relaxed rules.
2Manufacturing precision
If only certain aspects of IC design are reduced in size to match manufacturing improvements, then the benefits of manufacturing advances can be partially utilized, but the design revision process becomes complex and cumbersome
Solution Approach 1:
The system segments the IC design into different elements (conductive components, vias, spacing regions) and applies different transformation rules to each. It identifies which features can be safely reduced and which maintain original dimensions, automatically handling the complexity of selective size reduction across multiple design layers.
Solution Approach 2:
The system performs self-service by automatically analyzing the original IC design, identifying which features can be reduced, and applying the appropriate transformations without human intervention. It autonomously determines the optimal mix of reduced and original-size features based on the relaxed spacing rules.
3Productivity
If spacing between features is reduced to increase circuit density, then manufacturing efficiency improves, but the risk of short circuits and manufacturing defects increases
Solution Approach 1:
The system incorporates feedback mechanisms to verify that reduced spacing does not create short circuits or violate design rules. It checks the redesigned layout against manufacturing constraints and adjusts spacing as needed to maintain reliability while maximizing circuit density utilization of the improved manufacturing process.
Data Source
AI summary
Methods and systems access an original integrated circuit (IC) design. The smallest spacing between elements in the original IC design is an “original” minimum spacing. These methods and systems automatically convert the original IC design to a reduced IC design, and the smallest spacing between elements in the reduced IC design is a “reduced” minimum spacing that is less than the original minimum spacing. Such methods and systems either automatically replace a single via in the original IC design with multiple vias in the reduced IC design (in an area where the single via was located in the original IC design) or automatically replace the single via in the original IC design with a via bar in the reduced IC design (in an area where the single via was located in the original IC design).